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Move i2c to clash cores #2584

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c35889b
Move I2C example files to `clash-cores`
lmbollen Oct 3, 2023
9616fb2
Fix warnings in `i2c` core.
lmbollen Oct 3, 2023
14af81e
Add comments to i2c core
lmbollen Oct 10, 2023
c4bb357
Make I2C core polymorphic in its domain
lmbollen Oct 11, 2023
7bf0b2f
Remove HDL build test for I2C in examples
lmbollen Oct 18, 2023
5e0368e
Refactor i2c core to be more user friendly
lmbollen Oct 26, 2023
a1ce13e
Add I2C unit test to `clash-cores:unittests`
lmbollen Oct 31, 2023
c13627b
Respect boolean values of acknowledgements. Make acknowledgements com…
hiddemoll Jan 24, 2024
98e806c
Fix incorrect I2C test
hiddemoll Apr 9, 2024
28fdb7a
Refactor I2C core and unittest
hiddemoll Apr 9, 2024
0d2cbb7
Add debug flag to I2C unittest
hiddemoll Apr 9, 2024
ca4a097
Add module headers to all moved I2C modules
hiddemoll Apr 10, 2024
7676ced
Extend haddock documentation for I2C core
hiddemoll Apr 10, 2024
59cb3c7
Move I2C core to Experimental submodule
hiddemoll Apr 10, 2024
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14 changes: 7 additions & 7 deletions clash-cores/src/Clash/Cores/I2C/BitMaster.hs
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Expand Up @@ -70,13 +70,13 @@ bitMaster = exposeClockResetEnable (mealyB bitMasterT bitMasterInit)

bitMasterInit :: BitMasterS
bitMasterInit = BitS { _stateMachine = stateMachineStart
, _busState = busStartState
, _dout = high -- dout register
, _dsclOen = False -- delayed sclOen signal
, _clkEn = True -- statemachine clock enable
, _slaveWait = False -- clock generation signal
, _cnt = 0 -- clock divider counter (synthesis)
}
, _busState = busStartState
, _dout = high -- dout register
, _dsclOen = False -- delayed sclOen signal
, _clkEn = True -- statemachine clock enable
, _slaveWait = False -- clock generation signal
, _cnt = 0 -- clock divider counter (synthesis)
}


bitMasterT :: BitMasterS -> BitMasterI -> (BitMasterS, BitMasterO)
Expand Down
6 changes: 3 additions & 3 deletions clash-cores/src/Clash/Cores/I2C/ByteMaster.hs
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Expand Up @@ -138,7 +138,7 @@ byteMasterT s@(ByteS {_srState = ShiftRegister {..}, ..})

(Read, _) -> when coreAck $ do
shiftsr .= True
coreTxd .= (bitCoerce $ not ackRead)
coreTxd .= bitCoerce (not ackRead)
if cntDone then do
byteStateM .= Ack
coreCmd .= I2Cwrite
Expand All @@ -156,7 +156,7 @@ byteMasterT s@(ByteS {_srState = ShiftRegister {..}, ..})
byteStateM .= Stop
coreCmd .= I2Cstop
else
coreTxd .= (bitCoerce $ not ackRead)
coreTxd .= bitCoerce (not ackRead)

(Stop, _) -> when coreAck $ do
byteStateM .= Idle
Expand All @@ -166,6 +166,6 @@ byteMasterT s@(ByteS {_srState = ShiftRegister {..}, ..})
bitCtrl = (_coreCmd,_coreTxd)
i2cOpAck = (_byteStateM == Ack) && coreAck
ackWrite = i2cOpAck && not (bitCoerce coreRxd)
outp = (i2cOpAck,ackWrite,v2bv dout,bitCtrl)
outp = (i2cOpAck,ackWrite,v2bv dout,bitCtrl)

return outp
12 changes: 6 additions & 6 deletions clash-cores/test/Test/Cores/I2C.hs
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Expand Up @@ -15,13 +15,12 @@ import Test.Tasty.HUnit


system0 :: Clock System -> Reset System -> Signal System (Vec 16 (Unsigned 8), Bool, Bool)
system0 clk arst = bundle (registerFile,done,fault)
system0 clk arst = bundle (registerFile,i2cDone <$> confO,i2cFault <$> confO)
where
(_dout,hostAck,_busy,al,ackOut,i2cO) =
i2c clk arst rst (pure True) (pure 19) claim i2cOp (pure True) i2cI
i2c clk arst rst (pure True) (pure 19) (i2cClaim <$> confO) (i2cOp <$> confO) (pure True) i2cI

(claim,i2cOp,done,fault) =
unbundle $ config clk (bundle (rst,fmap not rst,hostAck,ackOut,al))
confO = config clk $ ConfI <$> rst <*> fmap not rst <*> hostAck <*> ackOut <*> al

(sclOut,sdaOut) = unbundle i2cO
scl = fmap (bitCoerce . isNothing) sclOut
Expand All @@ -44,8 +43,9 @@ systemResult :: (Vec 16 (Unsigned 8), Bool, Bool)
systemResult = L.last (sampleN 200050 system)

i2cTest :: TestTree
i2cTest = testCase "i2c core testcase passed"
$ assertBool "i2c core test procedure failed" (not fault)
i2cTest =
testCase "I2C" $
assertBool "I2C core test procedure failed" (not fault)
where
fault =
any (\(_,_,f) -> f) (takeWhile (\ (_, done, _) -> not done) $ sample system)
29 changes: 19 additions & 10 deletions clash-cores/test/Test/Cores/I2C/Config.hs
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Expand Up @@ -9,10 +9,10 @@ import Numeric (showHex)
import Clash.Cores.I2C.ByteMaster (I2COperation(..))

data ConfStateMachine = CONFena |
CONFaddr | CONFaddrAck |
CONFreg | CONFregAck |
CONFdata | CONFdataAck |
CONFstop
CONFaddr | CONFaddrAck |
CONFreg | CONFregAck |
CONFdata | CONFdataAck |
CONFstop
deriving Show

data ConfS = ConfS { i2cConfStateM :: ConfStateMachine
Expand All @@ -22,8 +22,18 @@ data ConfS = ConfS { i2cConfStateM :: ConfStateMachine
, i2cConfFault :: Bool
}

type ConfI = (Bool,Bool,Bool,Bool,Bool)
type ConfO = (Bool,Maybe I2COperation,Bool,Bool)
data ConfI = ConfI { i2cRst :: Bool
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The commit message just says "refactor", perhaps explain what the refactor does.

, i2cEna :: Bool
, i2cCmdAck :: Bool
, i2cRxAck :: Bool
, i2cAl :: Bool
}

data ConfO = ConfO { i2cClaim :: Bool
, i2cOp :: Maybe I2COperation
, i2cDone :: Bool
, i2cFault :: Bool
}

confInit :: ConfS
confInit = ConfS { i2cConfStateM = CONFena
Expand All @@ -37,13 +47,12 @@ configT
:: Reg ConfS
-> ConfI
-> SimIO ConfO
configT s0 (rst,ena,cmdAck,rxAck,al) = do
configT s0 ConfI{i2cRst=rst,i2cEna=ena,i2cCmdAck=cmdAck,i2cRxAck=rxAck,i2cAl=al} = do
s <- readReg s0
let ConfS confStateM claim i2cOp lutIndex fault = s
let ConfS confStateM claim op lutIndex fault = s

let i2cSlvAddr = 0x34 :: BitVector 8


let success = cmdAck && not al
done = lutIndex == 11

Expand Down Expand Up @@ -129,7 +138,7 @@ configT s0 (rst,ena,cmdAck,rxAck,al) = do
_ -> pure s

writeReg s0 sNext
pure (claim,i2cOp,done,fault)
pure $ ConfO claim op done fault

configLut :: Index 16 -> (BitVector 8, BitVector 8)
configLut i
Expand Down
73 changes: 44 additions & 29 deletions clash-cores/test/Test/Cores/I2C/Slave.hs
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Expand Up @@ -22,7 +22,15 @@ type ACConfTestI = (Bit,Bit)
type ACConfTestO = (Bit,Vec 16 (Unsigned 8))

i2cSlaveInit :: ACConfTestS
i2cSlaveInit = ACCTS (replicate d16 0x0) (replicate d8 0) 0 ATidle high high high 0
i2cSlaveInit = ACCTS { i2cSlaveRegFile = replicate d16 0x0
, i2cSlaveAddr = replicate d8 0
, i2cSlaveCntr = 0
, i2cSlaveAtStateM = ATidle
, i2cSlavePrevSCL = high
, i2cSlavePrevSDA = high
, i2cSlaveSdaOut = high
, i2cSlaveRegAddr = 0
}

i2cSlaveT :: Reg ACConfTestS -> ACConfTestI -> SimIO ACConfTestO
i2cSlaveT s0 (scl,sda) = do
Expand All @@ -45,19 +53,24 @@ i2cSlaveT s0 (scl,sda) = do
| cntr == 8 -> if validAddr then do
display "valid addr"
pure s { i2cSlaveAtStateM = ATaddrAck
, i2cSlaveAddr = repeat low
, i2cSlaveCntr = 0 }
, i2cSlaveAddr = repeat low
, i2cSlaveCntr = 0
}
else do
display "invalid addr"
display $ "invalid addr: " <> show addr
pure s { i2cSlaveAtStateM = ATidle
, i2cSlaveAddr = repeat low
, i2cSlaveCntr = 0}
| sclRising -> pure s { i2cSlaveCntr = cntr + 1
, i2cSlaveAddr = addr <<+ sda
, i2cSlaveSdaOut = high }
, i2cSlaveAddr = repeat low
, i2cSlaveCntr = 0
}
| sclRising -> pure s { i2cSlaveAddr = addr <<+ sda
, i2cSlaveCntr = cntr + 1
, i2cSlaveSdaOut = high
}
ATaddrAck
| sclRising -> do display "addrAck"
pure s { i2cSlaveAtStateM = ATreg, i2cSlaveSdaOut = low }
pure s { i2cSlaveAtStateM = ATreg
, i2cSlaveSdaOut = low
}
ATreg
| cntr == 8 -> if validRegAddr then do
display "valid reg addr"
Expand All @@ -67,39 +80,41 @@ i2cSlaveT s0 (scl,sda) = do
, i2cSlaveRegAddr = shiftR (bitCoerce addr) 1
}
else do
display "invalid reg addr"
display $ "invalid reg addr: " <> show addr
pure s { i2cSlaveAtStateM = ATidle
, i2cSlaveAddr = repeat low
, i2cSlaveCntr = 0
, i2cSlaveAddr = repeat low
, i2cSlaveCntr = 0
}
| sclRising -> pure s { i2cSlaveCntr = cntr + 1
, i2cSlaveAddr = addr <<+ sda
, i2cSlaveSdaOut = high }
| sclRising -> pure s { i2cSlaveAddr = addr <<+ sda
, i2cSlaveCntr = cntr + 1
, i2cSlaveSdaOut = high
}
ATregAck
| sclRising -> do display "regAck"
pure s { i2cSlaveSdaOut = low
, i2cSlaveAtStateM = ATval
pure s { i2cSlaveAtStateM = ATval
, i2cSlaveSdaOut = low
}
ATval
| cntr == 8 -> do display "val"
pure s { i2cSlaveAtStateM = ATvalAck
, i2cSlaveAddr = repeat low
, i2cSlaveCntr = 0
, i2cSlaveRegFile =
replace regAddr (bitCoerce addr) regFile
}
| sclRising -> pure s { i2cSlaveCntr = cntr + 1
, i2cSlaveAddr = addr <<+ sda
, i2cSlaveSdaOut = high }
, i2cSlaveAddr = repeat low
, i2cSlaveCntr = 0
, i2cSlaveRegFile =
replace regAddr (bitCoerce addr) regFile
}
| sclRising -> pure s { i2cSlaveAddr = addr <<+ sda
, i2cSlaveCntr = cntr + 1
, i2cSlaveSdaOut = high
}
ATvalAck
| sclRising -> do display "valAck"
pure s { i2cSlaveSdaOut = low
, i2cSlaveAtStateM = ATstop
pure s { i2cSlaveAtStateM = ATstop
, i2cSlaveSdaOut = low
}
ATstop
| stopCondition -> do display "stop"
pure s { i2cSlaveAtStateM = ATidle
, i2cSlaveSdaOut = high
, i2cSlaveSdaOut = high
}
_ -> pure s

Expand Down