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Merge tag 'socfpga_updates_for_v5.20_part2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/late
SoCFPGA dts updates for v5.20, part 2 - Update EMAC AXI settings for Cyclone5 * tag 'socfpga_updates_for_v5.20_part2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: dts: add EMAC AXI settings for Cyclone5 arm64: dts: altera: socfpga_stratix10: move clocks out of soc node arm64: dts: Add support for Stratix 10 Software Virtual Platform dt-bindings: altera: document Stratix 10 SWVP compatibles arm64: dts: altera: adjust whitespace around '=' arm64: dts: intel: socfpga_agilex: use defined GIC interrupt type for ECC dt-bindings: altera: Add Chameleon v3 board ARM: dts: socfpga: Add Google Chameleon v3 devicetree ARM: dts: socfpga: Add atsha204a node to Mercury+ AA1 dts ARM: dts: socfpga: Move sdmmc-ecc node to Arria 10 dts ARM: dts: socfpga: Change Mercury+ AA1 dts to dtsi Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2 parents 87df0ce + b3cbbb5 commit 0d98fbc

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‎Documentation/devicetree/bindings/arm/altera.yaml‎

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,14 @@ properties:
2525
items:
2626
- enum:
2727
- altr,socfpga-arria10-socdk
28-
- enclustra,mercury-aa1
28+
- const: altr,socfpga-arria10
29+
- const: altr,socfpga
30+
31+
- description: Mercury+ AA1 boards
32+
items:
33+
- enum:
34+
- google,chameleon-v3
35+
- const: enclustra,mercury-aa1
2936
- const: altr,socfpga-arria10
3037
- const: altr,socfpga
3138

@@ -47,6 +54,7 @@ properties:
4754
items:
4855
- enum:
4956
- altr,socfpga-stratix10-socdk
57+
- altr,socfpga-stratix10-swvp
5058
- const: altr,socfpga-stratix10
5159

5260
- description: SoCFPGA VT

‎arch/arm/boot/dts/Makefile‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1148,7 +1148,7 @@ dtb-$(CONFIG_ARCH_S5PV210) += \
11481148
s5pv210-torbreck.dtb
11491149
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
11501150
socfpga_arria5_socdk.dtb \
1151-
socfpga_arria10_mercury_aa1.dtb \
1151+
socfpga_arria10_chameleonv3.dtb \
11521152
socfpga_arria10_socdk_nand.dtb \
11531153
socfpga_arria10_socdk_qspi.dtb \
11541154
socfpga_arria10_socdk_sdmmc.dtb \

‎arch/arm/boot/dts/socfpga.dtsi‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -561,6 +561,12 @@
561561
interrupts = <0 175 4>;
562562
};
563563

564+
socfpga_axi_setup: stmmac-axi-config {
565+
snps,wr_osr_lmt = <0xf>;
566+
snps,rd_osr_lmt = <0xf>;
567+
snps,blen = <0 0 0 0 16 0 0>;
568+
};
569+
564570
gmac0: ethernet@ff700000 {
565571
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
566572
altr,sysmgr-syscon = <&sysmgr 0x60 0>;
@@ -576,6 +582,7 @@
576582
snps,perfect-filter-entries = <128>;
577583
tx-fifo-depth = <4096>;
578584
rx-fifo-depth = <4096>;
585+
snps,axi-config = <&socfpga_axi_setup>;
579586
status = "disabled";
580587
};
581588

@@ -594,6 +601,7 @@
594601
snps,perfect-filter-entries = <128>;
595602
tx-fifo-depth = <4096>;
596603
rx-fifo-depth = <4096>;
604+
snps,axi-config = <&socfpga_axi_setup>;
597605
status = "disabled";
598606
};
599607

‎arch/arm/boot/dts/socfpga_arria10.dtsi‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -736,6 +736,16 @@
736736
<37 IRQ_TYPE_LEVEL_HIGH>;
737737
};
738738

739+
sdmmca-ecc@ff8c2c00 {
740+
compatible = "altr,socfpga-sdmmc-ecc";
741+
reg = <0xff8c2c00 0x400>;
742+
altr,ecc-parent = <&mmc>;
743+
interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
744+
<47 IRQ_TYPE_LEVEL_HIGH>,
745+
<16 IRQ_TYPE_LEVEL_HIGH>,
746+
<48 IRQ_TYPE_LEVEL_HIGH>;
747+
};
748+
739749
dma-ecc@ff8c8000 {
740750
compatible = "altr,socfpga-dma-ecc";
741751
reg = <0xff8c8000 0x400>;

‎arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts‎

Lines changed: 90 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,90 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
/*
3+
* Copyright 2022 Google LLC
4+
*/
5+
/dts-v1/;
6+
#include "socfpga_arria10_mercury_aa1.dtsi"
7+
8+
/ {
9+
model = "Google Chameleon V3";
10+
compatible = "google,chameleon-v3", "enclustra,mercury-aa1",
11+
"altr,socfpga-arria10", "altr,socfpga";
12+
13+
aliases {
14+
serial0 = &uart0;
15+
i2c0 = &i2c0;
16+
i2c1 = &i2c1;
17+
};
18+
};
19+
20+
&gmac0 {
21+
status = "okay";
22+
};
23+
24+
&gpio0 {
25+
status = "okay";
26+
};
27+
28+
&gpio1 {
29+
status = "okay";
30+
};
31+
32+
&gpio2 {
33+
status = "okay";
34+
};
35+
36+
&i2c0 {
37+
status = "okay";
38+
39+
ssm2603: audio-codec@1a {
40+
compatible = "adi,ssm2603";
41+
reg = <0x1a>;
42+
};
43+
};
44+
45+
&i2c1 {
46+
status = "okay";
47+
48+
u80: gpio@21 {
49+
compatible = "nxp,pca9535";
50+
reg = <0x21>;
51+
gpio-controller;
52+
#gpio-cells = <2>;
53+
54+
gpio-line-names =
55+
"SOM_AUD_MUTE",
56+
"DP1_OUT_CEC_EN",
57+
"DP2_OUT_CEC_EN",
58+
"DP1_SOM_PS8469_CAD",
59+
"DPD_SOM_PS8469_CAD",
60+
"DP_OUT_PWR_EN",
61+
"STM32_RST_L",
62+
"STM32_BOOT0",
63+
64+
"FPGA_PROT",
65+
"STM32_FPGA_COMM0",
66+
"TP119",
67+
"TP120",
68+
"TP121",
69+
"TP122",
70+
"TP123",
71+
"TP124";
72+
};
73+
};
74+
75+
&mmc {
76+
status = "okay";
77+
};
78+
79+
&uart0 {
80+
status = "okay";
81+
};
82+
83+
&uart1 {
84+
status = "okay";
85+
};
86+
87+
&usb0 {
88+
status = "okay";
89+
dr_mode = "host";
90+
};

arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts renamed to arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi

Lines changed: 8 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,7 @@
11
// SPDX-License-Identifier: GPL-2.0
2-
/dts-v1/;
2+
/*
3+
* Copyright 2022 Google LLC
4+
*/
35

46
#include "socfpga_arria10.dtsi"
57

@@ -11,8 +13,6 @@
1113
aliases {
1214
ethernet0 = &gmac0;
1315
serial1 = &uart1;
14-
i2c0 = &i2c0;
15-
i2c1 = &i2c1;
1616
};
1717

1818
memory@0 {
@@ -26,24 +26,11 @@
2626
};
2727
};
2828

29-
&eccmgr {
30-
sdmmca-ecc@ff8c2c00 {
31-
compatible = "altr,socfpga-sdmmc-ecc";
32-
reg = <0xff8c2c00 0x400>;
33-
altr,ecc-parent = <&mmc>;
34-
interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
35-
<47 IRQ_TYPE_LEVEL_HIGH>,
36-
<16 IRQ_TYPE_LEVEL_HIGH>,
37-
<48 IRQ_TYPE_LEVEL_HIGH>;
38-
};
39-
};
40-
4129
&gmac0 {
4230
phy-mode = "rgmii";
4331
phy-addr = <0xffffffff>; /* probe for phy addr */
4432

4533
max-frame-size = <3800>;
46-
status = "okay";
4734

4835
phy-handle = <&phy3>;
4936

@@ -69,30 +56,20 @@
6956
};
7057
};
7158

72-
&gpio0 {
73-
status = "okay";
74-
};
75-
76-
&gpio1 {
77-
status = "okay";
78-
};
79-
80-
&gpio2 {
81-
status = "okay";
82-
};
83-
8459
&i2c1 {
85-
status = "okay";
60+
atsha204a: crypto@64 {
61+
compatible = "atmel,atsha204a";
62+
reg = <0x64>;
63+
};
64+
8665
isl12022: isl12022@6f {
87-
status = "okay";
8866
compatible = "isil,isl12022";
8967
reg = <0x6f>;
9068
};
9169
};
9270

9371
/* Following mappings are taken from arria10 socdk dts */
9472
&mmc {
95-
status = "okay";
9673
cap-sd-highspeed;
9774
broken-cd;
9875
bus-width = <4>;
@@ -101,12 +78,3 @@
10178
&osc1 {
10279
clock-frequency = <33330000>;
10380
};
104-
105-
&uart1 {
106-
status = "okay";
107-
};
108-
109-
&usb0 {
110-
status = "okay";
111-
dr_mode = "host";
112-
};

‎arch/arm64/Kconfig.platforms‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -248,7 +248,8 @@ config ARCH_INTEL_SOCFPGA
248248
bool "Intel's SoCFPGA ARMv8 Families"
249249
help
250250
This enables support for Intel's SoCFPGA ARMv8 families:
251-
Stratix 10 (ex. Altera), Agilex and eASIC N5X.
251+
Stratix 10 (ex. Altera), Stratix10 Software Virtual Platform,
252+
Agilex and eASIC N5X.
252253

253254
config ARCH_SYNQUACER
254255
bool "Socionext SynQuacer SoC Family"

‎arch/arm64/boot/dts/altera/Makefile‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,4 @@
11
# SPDX-License-Identifier: GPL-2.0-only
22
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_stratix10_socdk.dtb \
3-
socfpga_stratix10_socdk_nand.dtb
3+
socfpga_stratix10_socdk_nand.dtb \
4+
socfpga_stratix10_swvp.dtb

‎arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi‎

Lines changed: 29 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,34 @@
9797
<0x0 0xfffc6000 0x0 0x2000>;
9898
};
9999

100+
clocks {
101+
cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
102+
#clock-cells = <0>;
103+
compatible = "fixed-clock";
104+
};
105+
106+
cb_intosc_ls_clk: cb-intosc-ls-clk {
107+
#clock-cells = <0>;
108+
compatible = "fixed-clock";
109+
};
110+
111+
f2s_free_clk: f2s-free-clk {
112+
#clock-cells = <0>;
113+
compatible = "fixed-clock";
114+
};
115+
116+
osc1: osc1 {
117+
#clock-cells = <0>;
118+
compatible = "fixed-clock";
119+
};
120+
121+
qspi_clk: qspi-clk {
122+
#clock-cells = <0>;
123+
compatible = "fixed-clock";
124+
clock-frequency = <200000000>;
125+
};
126+
};
127+
100128
soc {
101129
#address-cells = <1>;
102130
#size-cells = <1>;
@@ -119,34 +147,6 @@
119147
#clock-cells = <1>;
120148
};
121149

122-
clocks {
123-
cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
124-
#clock-cells = <0>;
125-
compatible = "fixed-clock";
126-
};
127-
128-
cb_intosc_ls_clk: cb-intosc-ls-clk {
129-
#clock-cells = <0>;
130-
compatible = "fixed-clock";
131-
};
132-
133-
f2s_free_clk: f2s-free-clk {
134-
#clock-cells = <0>;
135-
compatible = "fixed-clock";
136-
};
137-
138-
osc1: osc1 {
139-
#clock-cells = <0>;
140-
compatible = "fixed-clock";
141-
};
142-
143-
qspi_clk: qspi-clk {
144-
#clock-cells = <0>;
145-
compatible = "fixed-clock";
146-
clock-frequency = <200000000>;
147-
};
148-
};
149-
150150
gmac0: ethernet@ff800000 {
151151
compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
152152
reg = <0xff800000 0x2000>;
@@ -594,7 +594,7 @@
594594
};
595595

596596
qspi: spi@ff8d2000 {
597-
compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
597+
compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
598598
#address-cells = <1>;
599599
#size-cells = <0>;
600600
reg = <0xff8d2000 0x100>,

‎arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts‎

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -52,12 +52,6 @@
5252
};
5353

5454
soc {
55-
clocks {
56-
osc1 {
57-
clock-frequency = <25000000>;
58-
};
59-
};
60-
6155
eccmgr {
6256
sdmmca-ecc@ff8c8c00 {
6357
compatible = "altr,socfpga-s10-sdmmc-ecc",
@@ -113,6 +107,10 @@
113107
bus-width = <4>;
114108
};
115109

110+
&osc1 {
111+
clock-frequency = <25000000>;
112+
};
113+
116114
&uart0 {
117115
status = "okay";
118116
};

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