Set priorities for issues 4376,4386,4390,4392,4393,4402,4408,4409,4412,4413 (simd)

xml/issue4375.xml

@@ -1,7 +1,7 @@
 <?xml version='1.0' encoding='utf-8' standalone='no'?>
 <!DOCTYPE issue SYSTEM "lwg-issue.dtd">
 
-<issue num="4375" status="New">
+<issue num="4375" status="Tentatively Ready">
 <title>`std::simd::bit_ceil` should not be `noexcept`</title>
 <section>
 <sref ref="[simd.bit]"/>
@@ -19,6 +19,11 @@
 <li><p>`std::bit_ceil` is not 'noexcept' (<sref ref="[bit.syn]"/> and <sref ref="[bit.pow.two]"/>) and</p></li>
 <li><p>`std::simd::bit_ceil` has a precondition.</p></li>
 </ol>
+
+<note>2025-10-22; Reflector poll.</note>
+<p>
+Set status to Tentatively Ready after six votes in favour during reflector poll.
+</p>
 </discussion>
 
 <resolution>

xml/issue4386.xml

@@ -9,7 +9,7 @@
 </section>
 <submitter>Hewill Kang</submitter>
 <date>27 Sep 2025</date>
-<priority>99</priority>
+<priority>3</priority>
 
 <discussion>
 <p>
@@ -20,6 +20,16 @@ Given that it seems intended to work with `basic_vec`, `basic_mask`, or vectoriz
 requiring `T` and `U` to be copyable seems reasonable since they are trivially copyable. 
 It shouldn't take non-copyable objects and produce hard errors in the function body.
 </p>
+
+<note>2025-10-22; Reflector poll.</note>
+<p>
+Set priority to 3 after reflector poll.
+</p>
+<p>
+Split opinion between further pinning down exact condition (<tt>is_constructible_v</tt>,
+<tt>decltype(auto(c ? a : b))</tt>), and accepting the PR (<tt>copyable</tt>) as this is
+not meant to be generic facility.
+</p>
 </discussion>
 
 <resolution>

xml/issue4390.xml

@@ -1,12 +1,12 @@
 <?xml version='1.0' encoding='utf-8' standalone='no'?>
 <!DOCTYPE issue SYSTEM "lwg-issue.dtd">
 
-<issue num="4390" status="New">
+<issue num="4390" status="LEWG">
 <title><code>simd::basic_vec(U&amp;&amp;)</code> default template parameter</title>
 <section><sref ref="[simd.ctor]"/></section>
 <submitter>Hewill Kang</submitter>
 <date>29 Sep 2025</date>
-<priority>99</priority>
+<priority>4</priority>
 
 <discussion>
 <p>
@@ -17,6 +17,17 @@ intuitive spelling:
 <pre>
 simd::vec&lt;complex&lt;double&gt;&gt; sc1   ({-1.0, 0.5}); // <span style="color:#C80000;font-weight:bold">current ill-formed</span>
 simd::vec&lt;complex&lt;double&gt;&gt; sc2 = {{-1.0, 0.5}}; // <span style="color:#C80000;font-weight:bold">current ill-formed</span></pre>
+
+<note>2025-10-22; Reflector poll. Status changed: New &rarr; LEWG with priority 4.</note>
+
+<p>
+This narrows design space wrt using braces for initialization
+of <tt>basic_vec</tt>, especially if we allow user-defined types.
+</p>
+<p>
+LWG <iref ref="4230"/> would address this by allowing
+<tt>vec&lt;complex&lt;double&gt;&gt;(1., 1.);</tt>
+</p>
 </discussion>
 
 <resolution>

xml/issue4392.xml

@@ -6,7 +6,7 @@
 <section><sref ref="[simd.loadstore]"/></section>
 <submitter>Hewill Kang</submitter>
 <date>29 Sep 2025</date>
-<priority>99</priority>
+<priority>3</priority>
 
 <discussion>
 <p>
@@ -16,6 +16,15 @@ Currently, `simd::unchecked_load`/`partial_load`/`unchecked_store`/`partial_stor
 However, the construction is ill-formed when the difference type is an integer-class type; we should perform
 an explicit casting here.
 </p>
+
+<note>2025-10-22; Reflector poll.</note>
+<p>
+Set priority to 3 after reflector poll.
+</p>
+<p>
+Question was raised if we should use <tt>size_t</tt> instead of
+<tt>iter_difference_t</tt> for consistency with <tt>span</tt>.
+</p>
 </discussion>
 
 <resolution>

xml/issue4393.xml

@@ -6,7 +6,7 @@
 <section><sref ref="[simd.permute.memory]"/></section>
 <submitter>Hewill Kang</submitter>
 <date>29 Sep 2025</date>
-<priority>99</priority>
+<priority>2</priority>
 
 <discussion>
 <p>
@@ -17,6 +17,16 @@ However, they only require `R` to be `contiguous_range` and `sized_range`.
 Requiring `R` to be `output_range` is also necessary; otherwise, the 
 `constant_range` cannot be written.
 </p>
+
+<note>2025-10-22; Reflector poll.</note>
+<p>
+Set priority to 2 after reflector poll.
+</p>
+<p>
+This issue is related to LWG <iref ref="4420"/>.
+The <i>Constrains</i> needs to be updated to handle conversions between <tt>float</tt>
+and <tt>float16_t</tt> and similar cases.  
+</p>
 </discussion>
 
 <resolution>

xml/issue4402.xml

@@ -8,7 +8,7 @@
 </section>
 <submitter>Arthur O'Dwyer</submitter>
 <date>02 Oct 2025</date>
-<priority>99</priority>
+<priority>3</priority>
 
 <discussion>
 <p>
@@ -62,6 +62,21 @@ class <tt><i>simd-iterator</i></tt> and/or remove the "exposition only" from <tt
 constructor. That makes it clear that the above program is indeed intended to be ambiguous. But IMO 
 we should instead simply make the above program valid.
 </p>
+
+<note>2025-10-22; Reflector poll.</note>
+<p>
+Set priority to 3 after reflector poll.
+</p>
+<p>
+<tt><i>simd-iterator</i></tt> can only be constructed only by <tt>basic_vec</tt>,
+and <tt>basic_mask</tt> objects.
+</p>
+<p>
+This is NAD as user cannot rely on standard types not being constructible per
+<sref ref="[member.functions]"/> p2. The example would not be fixed by adding
+the <tt>explicit</tt> in a conforming implementation, and changes in <tt>return</tt>
+specification are editorial.
+</p>
 </discussion>
 
 <resolution>

xml/issue4408.xml

@@ -1,21 +1,23 @@
 <?xml version='1.0' encoding='utf-8' standalone='no'?>
 <!DOCTYPE issue SYSTEM "lwg-issue.dtd">
 
-<issue num="4408" status="New">
+<issue num="4408" status="LEWG">
 <title>Hardening `simd::vec::operator[]`</title>
 <section>
 <sref ref="[simd.subscr]"/>
 <sref ref="[simd.mask.subscr]"/>
 </section>
 <submitter>Hewill Kang</submitter>
 <date>07 Oct 2025</date>
-<priority>99</priority>
+<priority>3</priority>
 
 <discussion>
 <p>
 `simd::vec::operator[]` satisfies the criteria in <paper num="P3471R4"/> and <paper num="P3697R1"/> : 
 "violating the precondition results in a memory safety issue", which means that hardening is reasonable.
 </p>
+
+<note>2025-10-22; Reflector poll. Status changed: New &rarr; LEWG and P3.</note>
 </discussion>
 
 <resolution>

xml/issue4409.xml

@@ -8,7 +8,7 @@
 </section>
 <submitter>Lénárd Szolnoki</submitter>
 <date>10 Oct 2025</date>
-<priority>99</priority>
+<priority>3</priority>
 
 <discussion>
 <p>
@@ -81,6 +81,15 @@ down in the preconditions).
 </li>
 </ol>
 
+
+<note>2025-10-22; Reflector poll.</note>
+<p>
+Set priority to P3 after reflector poll.
+</p>
+<p>
+General preference on considering this NAD, and instead clarifying that
+operations on integer-class should produce constant expressions.
+</p>
 </discussion>
 
 <resolution>

xml/issue4412.xml

@@ -1,7 +1,7 @@
 <?xml version='1.0' encoding='utf-8' standalone='no'?>
 <!DOCTYPE issue SYSTEM "lwg-issue.dtd">
 
-<issue num="4412" status="New">
+<issue num="4412" status="Tentatively Ready">
 <title>Fix declaration of `zero_element` and `uninit_element`</title>
 <section><sref ref="[simd.syn]"/></section>
 <submitter>Jonathan Wakely</submitter>
@@ -14,6 +14,11 @@
 <p>
 `zero_element` and `uninit_element` should be inline and not static
 </p>
+
+<note>2025-10-22; Reflector poll.</note>
+<p>
+Set status to Tentatively Ready after seven votes in favour during reflector poll.
+</p>
 </discussion>
 
 <resolution>

xml/issue4413.xml

@@ -1,7 +1,7 @@
 <?xml version='1.0' encoding='utf-8' standalone='no'?>
 <!DOCTYPE issue SYSTEM "lwg-issue.dtd">
 
-<issue num="4413" status="New">
+<issue num="4413" status="Tentatively Ready">
 <title>Unused/left-over `simd::alignment` specialization for `basic_mask`</title>
 <section><sref ref="[simd.traits]"/></section>
 <submitter>Matthias Kretz</submitter>
@@ -16,6 +16,11 @@ This was used for loads and stores for masks from/to arrays of `bool`.
 However, these load/store functions were removed after `bitset`/`unsigned_integral` 
 conversions were introduced. This left-over TS wording should be removed.
 </p>
+
+<note>2025-10-22; Reflector poll.</note>
+<p>
+Set status to Tentatively Ready after seven votes in favour during reflector poll.
+</p>
 </discussion>
 
 <resolution>