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rwk-gitLorenzo Pieralisi
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PCI: rockchip: Write PCI Device ID to correct register
Write PCI Device ID (DID) to the correct register. The Device ID was not updated through the correct register. Device ID was written to a read-only register and therefore did not work. The Device ID is now set through the correct register. This is documented in the RK3399 TRM section 17.6.6.1.1 Link: https://lore.kernel.org/r/[email protected] Fixes: cf590b0 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller") Tested-by: Damien Le Moal <[email protected]> Signed-off-by: Rick Wertenbroek <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Damien Le Moal <[email protected]> Cc: [email protected]
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drivers/pci/controller/pcie-rockchip-ep.c

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -115,6 +115,7 @@ static void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn,
115115
static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn,
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struct pci_epf_header *hdr)
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{
118+
u32 reg;
118119
struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
119120
struct rockchip_pcie *rockchip = &ep->rockchip;
120121

@@ -127,8 +128,9 @@ static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn,
127128
PCIE_CORE_CONFIG_VENDOR);
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}
129130

130-
rockchip_pcie_write(rockchip, hdr->deviceid << 16,
131-
ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_VENDOR_ID);
131+
reg = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_DID_VID);
132+
reg = (reg & 0xFFFF) | (hdr->deviceid << 16);
133+
rockchip_pcie_write(rockchip, reg, PCIE_EP_CONFIG_DID_VID);
132134

133135
rockchip_pcie_write(rockchip,
134136
hdr->revid |

drivers/pci/controller/pcie-rockchip.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -133,6 +133,8 @@
133133
#define PCIE_RC_RP_ATS_BASE 0x400000
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#define PCIE_RC_CONFIG_NORMAL_BASE 0x800000
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#define PCIE_RC_CONFIG_BASE 0xa00000
136+
#define PCIE_EP_CONFIG_BASE 0xa00000
137+
#define PCIE_EP_CONFIG_DID_VID (PCIE_EP_CONFIG_BASE + 0x00)
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#define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
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#define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4)
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#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18

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