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Ben Skeggsairlied
Ben Skeggs
authored and
airlied
committed
drm/nouveau: add support for GB20x
This commit adds support for the GB20x GPUs found on GeForce RTX 50xx series boards. Beyond a few miscellaneous register moves and HW class ID plumbing, this reuses most of the code added to support GH100/GB10x. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Timur Tabi <[email protected]> Tested-by: Timur Tabi <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
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‎drivers/gpu/drm/nouveau/include/nvhw/ref/gb10b/dev_fbhub.h‎

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/* SPDX-License-Identifier: MIT
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*
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* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef __gb10b_dev_fb_h__
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#define __gb10b_dev_fb_h__
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#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO 0x008a1d58 /* RW-4R */
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#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR 31:0 /* RWIVF */
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#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_INIT 0x00000000 /* RWI-V */
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#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_MASK 0xffffff00 /* RW--V */
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#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI 0x008a1d5c /* RW-4R */
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#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */
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#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_INIT 0x00000000 /* RWI-V */
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#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000fffff /* RW--V */
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#endif // __gb10b_dev_fb_h__
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‎drivers/gpu/drm/nouveau/include/nvhw/ref/gb202/dev_ce.h‎

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/* SPDX-License-Identifier: MIT
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*
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* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef __gb202_dev_ce_h__
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#define __gb202_dev_ce_h__
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#define NV_CE_GRCE_MASK 0x001040d8 /* C--4R */
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#define NV_CE_GRCE_MASK_VALUE 9:0 /* C--VF */
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#define NV_CE_GRCE_MASK_VALUE_INIT 0x00f /* C---V */
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#endif // __gb202_dev_ce_h__

‎drivers/gpu/drm/nouveau/include/nvhw/ref/gb202/dev_therm.h‎

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/* SPDX-License-Identifier: MIT
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*
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* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef __gb202_dev_therm_h__
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#define __gb202_dev_therm_h__
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#define NV_THERM_I2CS_SCRATCH 0x00ad00bc /* RW-4R */
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#define NV_THERM_I2CS_SCRATCH_DATA 31:0 /* RWIVF */
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#define NV_THERM_I2CS_SCRATCH_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE NV_THERM_I2CS_SCRATCH
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#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS 31:0
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#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_SUCCESS 0x000000FF
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#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_FAILED 0x00000000
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#endif // __gb202_dev_therm_h__
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‎drivers/gpu/drm/nouveau/include/nvif/class.h‎

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Original file line numberDiff line numberDiff line change
@@ -65,6 +65,7 @@
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#define TURING_USERMODE_A 0x0000c461
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#define AMPERE_USERMODE_A 0x0000c561
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#define HOPPER_USERMODE_A 0x0000c661
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#define BLACKWELL_USERMODE_A 0x0000c761
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#define MAXWELL_FAULT_BUFFER_A /* clb069.h */ 0x0000b069
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#define VOLTA_FAULT_BUFFER_A /* clb069.h */ 0x0000c369
@@ -89,6 +90,7 @@
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#define AMPERE_CHANNEL_GPFIFO_B /* if0020.h */ 0x0000c76f
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#define HOPPER_CHANNEL_GPFIFO_A 0x0000c86f
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#define BLACKWELL_CHANNEL_GPFIFO_A 0x0000c96f
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#define BLACKWELL_CHANNEL_GPFIFO_B 0x0000ca6f
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#define NV50_DISP /* if0010.h */ 0x00005070
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#define G82_DISP /* if0010.h */ 0x00008270
@@ -106,8 +108,10 @@
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#define TU102_DISP /* if0010.h */ 0x0000c570
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#define GA102_DISP /* if0010.h */ 0x0000c670
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#define AD102_DISP /* if0010.h */ 0x0000c770
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#define GB202_DISP 0x0000ca70
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#define GV100_DISP_CAPS 0x0000c373
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#define GB202_DISP_CAPS 0x0000ca73
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#define NV31_MPEG 0x00003174
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#define G82_MPEG 0x00008274
@@ -122,6 +126,7 @@
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#define GV100_DISP_CURSOR /* if0014.h */ 0x0000c37a
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#define TU102_DISP_CURSOR /* if0014.h */ 0x0000c57a
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#define GA102_DISP_CURSOR /* if0014.h */ 0x0000c67a
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#define GB202_DISP_CURSOR 0x0000ca7a
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#define NV50_DISP_OVERLAY /* if0014.h */ 0x0000507b
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#define G82_DISP_OVERLAY /* if0014.h */ 0x0000827b
@@ -132,6 +137,7 @@
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#define GV100_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c37b
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#define TU102_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c57b
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#define GA102_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c67b
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#define GB202_DISP_WINDOW_IMM_CHANNEL_DMA 0x0000ca7b
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#define NV50_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000507c
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#define G82_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000827c
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#define TU102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c57d
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#define GA102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c67d
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#define AD102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c77d
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#define GB202_DISP_CORE_CHANNEL_DMA 0x0000ca7d
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#define NV50_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000507e
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#define G82_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000827e
@@ -168,6 +175,7 @@
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#define GV100_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c37e
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#define TU102_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c57e
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#define GA102_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c67e
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#define GB202_DISP_WINDOW_CHANNEL_DMA 0x0000ca7e
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#define NV50_TESLA 0x00005097
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#define G82_TESLA 0x00008297
@@ -201,6 +209,7 @@
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#define HOPPER_A 0x0000cb97
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#define BLACKWELL_A 0x0000cd97
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#define BLACKWELL_B 0x0000ce97
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#define NV74_BSP 0x000074b0
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@@ -210,6 +219,7 @@
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#define NVC7B0_VIDEO_DECODER 0x0000c7b0
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#define NVC9B0_VIDEO_DECODER 0x0000c9b0
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#define NVCDB0_VIDEO_DECODER 0x0000cdb0
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#define NVCFB0_VIDEO_DECODER 0x0000cfb0
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#define GT212_MSVLD 0x000085b1
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#define IGT21A_MSVLD 0x000086b1
@@ -240,10 +250,12 @@
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#define AMPERE_DMA_COPY_B 0x0000c7b5
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#define HOPPER_DMA_COPY_A 0x0000c8b5
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#define BLACKWELL_DMA_COPY_A 0x0000c9b5
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#define BLACKWELL_DMA_COPY_B 0x0000cab5
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#define NVC4B7_VIDEO_ENCODER 0x0000c4b7
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#define NVC7B7_VIDEO_ENCODER 0x0000c7b7
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#define NVC9B7_VIDEO_ENCODER 0x0000c9b7
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#define NVCFB7_VIDEO_ENCODER 0x0000cfb7
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#define FERMI_DECOMPRESS 0x000090b8
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@@ -264,17 +276,20 @@
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#define ADA_COMPUTE_A 0x0000c9c0
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#define HOPPER_COMPUTE_A 0x0000cbc0
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#define BLACKWELL_COMPUTE_A 0x0000cdc0
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#define BLACKWELL_COMPUTE_B 0x0000cec0
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#define NV74_CIPHER 0x000074c1
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#define NVB8D1_VIDEO_NVJPG 0x0000b8d1
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#define NVC4D1_VIDEO_NVJPG 0x0000c4d1
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#define NVC9D1_VIDEO_NVJPG 0x0000c9d1
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#define NVCDD1_VIDEO_NVJPG 0x0000cdd1
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#define NVCFD1_VIDEO_NVJPG 0x0000cfd1
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#define NVB8FA_VIDEO_OFA 0x0000b8fa
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#define NVC6FA_VIDEO_OFA 0x0000c6fa
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#define NVC7FA_VIDEO_OFA 0x0000c7fa
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#define NVC9FA_VIDEO_OFA 0x0000c9fa
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#define NVCDFA_VIDEO_OFA 0x0000cdfa
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#define NVCFFA_VIDEO_OFA 0x0000cffa
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#endif

‎drivers/gpu/drm/nouveau/include/nvkm/core/device.h‎

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@@ -49,6 +49,7 @@ struct nvkm_device {
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GH100 = 0x180,
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AD100 = 0x190,
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GB10x = 0x1a0,
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GB20x = 0x1b0,
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} card_type;
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u32 chipset;
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u8 chiprev;

‎drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h‎

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@@ -104,6 +104,7 @@ int ga100_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct n
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int ga102_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
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int gh100_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
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int gb100_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
107+
int gb202_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
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#include <subdev/bios.h>
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#include <subdev/bios/ramcfg.h>

‎drivers/gpu/drm/nouveau/include/nvkm/subdev/fsp.h‎

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@@ -20,4 +20,5 @@ int nvkm_fsp_boot_gsp_fmc(struct nvkm_fsp *, u64 args_addr, u32 rsvd_size, bool
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int gh100_fsp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fsp **);
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int gb100_fsp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fsp **);
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int gb202_fsp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fsp **);
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#endif

‎drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h‎

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@@ -493,4 +493,5 @@ int ga102_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_
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int gh100_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gsp **);
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int ad102_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gsp **);
495495
int gb100_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gsp **);
496+
int gb202_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gsp **);
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#endif

‎drivers/gpu/drm/nouveau/nouveau_bo.c‎

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@@ -1000,6 +1000,7 @@ nouveau_bo_move_init(struct nouveau_drm *drm)
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struct ttm_resource *, struct ttm_resource *);
10011001
int (*init)(struct nouveau_channel *, u32 handle);
10021002
} _methods[] = {
1003+
{ "COPY", 4, 0xcab5, nve0_bo_move_copy, nve0_bo_move_init },
10031004
{ "COPY", 4, 0xc9b5, nve0_bo_move_copy, nve0_bo_move_init },
10041005
{ "COPY", 4, 0xc8b5, nve0_bo_move_copy, nve0_bo_move_init },
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{ "COPY", 4, 0xc7b5, nve0_bo_move_copy, nve0_bo_move_init },

‎drivers/gpu/drm/nouveau/nouveau_chan.c‎

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@@ -249,6 +249,7 @@ nouveau_channel_ctor(struct nouveau_cli *cli, bool priv, u64 runm,
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struct nouveau_channel **pchan)
250250
{
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const struct nvif_mclass hosts[] = {
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{ BLACKWELL_CHANNEL_GPFIFO_B, 0 },
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{ BLACKWELL_CHANNEL_GPFIFO_A, 0 },
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{ HOPPER_CHANNEL_GPFIFO_A, 0 },
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{ AMPERE_CHANNEL_GPFIFO_B, 0 },

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