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bebarinobebarino
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Merge branches 'clk-counted', 'clk-imx', 'clk-amlogic', 'clk-binding' and 'clk-rockchip' into clk-next
* clk-counted: clk: bcm: rpi: Assign ->num before accessing ->hws clk: bcm: dvp: Assign ->num before accessing ->hws * clk-imx: clk: imx: imx8mp: Convert to platform remove callback returning void clk: imx: imx8mp: Switch to RUNTIME_PM_OPS() clk: imx: add i.MX95 BLK CTL clk driver dt-bindings: clock: support i.MX95 Display Master CSR module dt-bindings: clock: support i.MX95 BLK CTL module dt-bindings: clock: add i.MX95 clock header clk: imx: imx8mp: Add pm_runtime support for power saving * clk-amlogic: clk: meson: s4: fix module autoloading clk: meson: fix module license to GPL only clk: meson: g12a: make VCLK2 and ENCL clock path configurable by CCF clk: meson: add vclk driver clk: meson: pll: print out pll name when unable to lock it clk: meson: s4: pll: determine maximum register in regmap config clk: meson: s4: peripherals: determine maximum register in regmap config clk: meson: a1: pll: determine maximum register in regmap config clk: meson: a1: peripherals: determine maximum register in regmap config * clk-binding: dt-bindings: clock: fixed: Define a preferred node name * clk-rockchip: clk: rockchip: rk3568: Add PLL rate for 724 MHz clk: rockchip: Remove an unused field in struct rockchip_mmc_clock clk: rockchip: rk3588: Add reset line for HDMI Receiver clk: rockchip: rk3568: Add missing USB480M_PHY mux dt-bindings: reset: Define reset id used for HDMI Receiver dt-bindings: clock: rockchip: add USB480M_PHY mux
6 parents 7552d1b + 6dc445c + 16fb217 + d855571 + b3e9912 + 2f8acf7 commit 4a35e6f

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‎Documentation/devicetree/bindings/clock/fixed-clock.yaml‎

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@@ -11,6 +11,15 @@ maintainers:
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- Stephen Boyd <[email protected]>
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properties:
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$nodename:
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anyOf:
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- description:
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Preferred name is 'clock-<freq>' with <freq> being the output
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frequency as defined in the 'clock-frequency' property.
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pattern: "^clock-([0-9]+|[a-z0-9-]+)$"
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- description: Any name allowed
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deprecated: true
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compatible:
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const: fixed-clock
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‎Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml‎

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@@ -11,6 +11,15 @@ maintainers:
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- Stephen Boyd <[email protected]>
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properties:
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$nodename:
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anyOf:
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- description:
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If the frequency is fixed, the preferred name is 'clock-<freq>' with
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<freq> being the output frequency.
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pattern: "^clock-([0-9]+|[0-9a-z-]+)$"
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- description: Any name allowed
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deprecated: true
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compatible:
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enum:
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- fixed-factor-clock

‎Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/nxp,imx95-blk-ctl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX95 Block Control
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maintainers:
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- Peng Fan <[email protected]>
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properties:
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compatible:
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items:
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- enum:
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- nxp,imx95-lvds-csr
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- nxp,imx95-display-csr
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- nxp,imx95-camera-csr
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- nxp,imx95-vpu-csr
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- const: syscon
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reg:
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maxItems: 1
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power-domains:
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maxItems: 1
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clocks:
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maxItems: 1
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'#clock-cells':
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const: 1
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description:
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. See
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include/dt-bindings/clock/nxp,imx95-clock.h
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required:
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- compatible
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- reg
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- '#clock-cells'
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- power-domains
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- clocks
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additionalProperties: false
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examples:
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- |
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syscon@4c410000 {
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compatible = "nxp,imx95-vpu-csr", "syscon";
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reg = <0x4c410000 0x10000>;
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#clock-cells = <1>;
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clocks = <&scmi_clk 114>;
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power-domains = <&scmi_devpd 21>;
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};
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...

‎Documentation/devicetree/bindings/clock/nxp,imx95-display-master-csr.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/nxp,imx95-display-master-csr.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX95 Display Master Block Control
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maintainers:
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- Peng Fan <[email protected]>
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properties:
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compatible:
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items:
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- const: nxp,imx95-display-master-csr
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- const: syscon
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reg:
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maxItems: 1
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power-domains:
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maxItems: 1
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clocks:
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maxItems: 1
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'#clock-cells':
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const: 1
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description:
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. See
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include/dt-bindings/clock/nxp,imx95-clock.h
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mux-controller:
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type: object
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$ref: /schemas/mux/reg-mux.yaml
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required:
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- compatible
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- reg
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- '#clock-cells'
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- mux-controller
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- power-domains
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- clocks
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additionalProperties: false
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examples:
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- |
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syscon@4c410000 {
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compatible = "nxp,imx95-display-master-csr", "syscon";
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reg = <0x4c410000 0x10000>;
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#clock-cells = <1>;
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clocks = <&scmi_clk 62>;
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power-domains = <&scmi_devpd 3>;
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mux: mux-controller {
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compatible = "mmio-mux";
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#mux-control-cells = <1>;
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mux-reg-masks = <0x4 0x00000001>; /* Pixel_link_sel */
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idle-states = <0>;
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};
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};
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...

‎drivers/clk/bcm/clk-bcm2711-dvp.c‎

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@@ -56,6 +56,8 @@ static int clk_dvp_probe(struct platform_device *pdev)
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if (ret)
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return ret;
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data->num = NR_CLOCKS;
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data->hws[0] = clk_hw_register_gate_parent_data(&pdev->dev,
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"hdmi0-108MHz",
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&clk_dvp_parent, 0,
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goto unregister_clk0;
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}
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data->num = NR_CLOCKS;
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ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
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data);
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if (ret)

‎drivers/clk/bcm/clk-raspberrypi.c‎

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@@ -371,8 +371,8 @@ static int raspberrypi_discover_clocks(struct raspberrypi_clk *rpi,
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if (IS_ERR(hw))
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return PTR_ERR(hw);
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data->hws[clks->id] = hw;
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data->num = clks->id + 1;
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data->hws[clks->id] = hw;
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}
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clks++;

‎drivers/clk/imx/Kconfig‎

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@@ -114,6 +114,13 @@ config CLK_IMX93
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help
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Build the driver for i.MX93 CCM Clock Driver
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config CLK_IMX95_BLK_CTL
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tristate "IMX95 Clock Driver for BLK CTL"
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depends on ARCH_MXC || COMPILE_TEST
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select MXC_CLK
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help
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Build the clock driver for i.MX95 BLK CTL
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config CLK_IMXRT1050
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tristate "IMXRT1050 CCM Clock Driver"
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depends on SOC_IMXRT || COMPILE_TEST

‎drivers/clk/imx/Makefile‎

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@@ -31,6 +31,7 @@ obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-imx8mp-audiomix.o
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obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
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obj-$(CONFIG_CLK_IMX93) += clk-imx93.o
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obj-$(CONFIG_CLK_IMX95_BLK_CTL) += clk-imx95-blk-ctl.o
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obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o clk-imx-acm.o
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clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o \

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