Merge branches 'clk-remove', 'clk-amlogic', 'clk-qcom', 'clk-parent' and 'clk-microchip' into clk-next

* clk-remove:
  clk: starfive: jh7110-vout: Convert to platform remove callback returning void
  clk: starfive: jh7110-isp: Convert to platform remove callback returning void
  clk: imx: imx8-acm: Convert to platform remove callback returning void

* clk-amlogic:
  clk: meson: Add missing clocks to axg_clk_regmaps

* clk-qcom: (62 commits)
  clk: qcom: gcc-ipq5018: fix register offset for GCC_UBI0_AXI_ARES reset
  clk: qcom: gcc-ipq5018: fix 'halt_reg' offset of 'gcc_pcie1_pipe_clk'
  clk: qcom: gcc-ipq5018: fix 'enable_reg' offset of 'gcc_gmac0_sys_clk'
  clk: qcom: camcc-x1e80100: Fix missing DT_IFACE enum in x1e80100 camcc
  clk: qcom: mmcc-msm8974: fix terminating of frequency table arrays
  clk: qcom: mmcc-apq8084: fix terminating of frequency table arrays
  clk: qcom: camcc-sc8280xp: fix terminating of frequency table arrays
  clk: qcom: gcc-ipq9574: fix terminating of frequency table arrays
  clk: qcom: gcc-ipq8074: fix terminating of frequency table arrays
  clk: qcom: gcc-ipq6018: fix terminating of frequency table arrays
  clk: qcom: gcc-ipq5018: fix terminating of frequency table arrays
  clk: qcom: dispcc-sdm845: Adjust internal GDSC wait times
  dt-bindings: clk: qcom: drop the SC7180 Modem subsystem clock controller
  clk: qcom: drop the SC7180 Modem subsystem clock driver
  clk: qcom: Use qcom_branch_set_clk_en()
  clk: qcom: branch: Add a helper for setting the enable bit
  clk: qcom: dispcc-sm8250: Make clk_init_data and pll_vco const
  clk: qcom: gcc-sc8180x: Add missing UFS QREF clocks
  clk: qcom: gcc-msm8953: add more resets
  clk: qcom: videocc-*: switch to module_platform_driver
  ...

* clk-parent:
  clk: Fix clk_core_get NULL dereference

* clk-microchip:
  clk: microchip: mpfs: convert MSSPLL outputs to clk_divider
  clk: microchip: mpfs: add missing MSSPLL outputs
  clk: microchip: mpfs: setup for using other mss pll outputs
  clk: microchip: mpfs: split MSSPLL in two
  dt-bindings: can: mpfs: add missing required clock
  dt-bindings: clock: mpfs: add more MSSPLL output definitions

Author: bebarino

Documentation/devicetree/bindings/clock/qcom,gpucc.yaml

@@ -53,6 +53,9 @@ properties:
   power-domains:
     maxItems: 1
 
+  vdd-gfx-supply:
+    description: Regulator supply for the VDD_GFX pads
+
   '#clock-cells':
     const: 1
 
@@ -74,6 +77,12 @@ required:
   - '#reset-cells'
   - '#power-domain-cells'
 
+# Require that power-domains and vdd-gfx-supply are not both present
+not:
+  required:
+    - power-domains
+    - vdd-gfx-supply
+
 additionalProperties: false
 
 examples:

Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml

@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Q6SSTOP clock Controller
 
 maintainers:
-  - Govind Singh <govinds@codeaurora.org>
+  - Bjorn Andersson <andersson@kernel.org>
 
 properties:
   compatible:

Documentation/devicetree/bindings/clock/qcom,sc7180-mss.yaml

@@ -17,6 +17,7 @@ description: |
     include/dt-bindings/clock/qcom,sm8450-camcc.h
     include/dt-bindings/clock/qcom,sm8550-camcc.h
     include/dt-bindings/clock/qcom,sc8280xp-camcc.h
+    include/dt-bindings/clock/qcom,x1e80100-camcc.h
 
 allOf:
   - $ref: qcom,gcc.yaml#
@@ -27,6 +28,7 @@ properties:
       - qcom,sc8280xp-camcc
       - qcom,sm8450-camcc
       - qcom,sm8550-camcc
+      - qcom,x1e80100-camcc
 
   clocks:
     items:

Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml

@@ -18,13 +18,15 @@ description: |
     include/dt-bindings/clock/qcom,sm8550-gpucc.h
     include/dt-bindings/reset/qcom,sm8450-gpucc.h
     include/dt-bindings/reset/qcom,sm8650-gpucc.h
+    include/dt-bindings/reset/qcom,x1e80100-gpucc.h
 
 properties:
   compatible:
     enum:
       - qcom,sm8450-gpucc
       - qcom,sm8550-gpucc
       - qcom,sm8650-gpucc
+      - qcom,x1e80100-gpucc
 
   clocks:
     items:

Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml

@@ -14,12 +14,17 @@ description: |
   Qualcomm display clock control module provides the clocks, resets and power
   domains on SM8550.
 
-  See also:: include/dt-bindings/clock/qcom,sm8550-dispcc.h
+  See also:
+  - include/dt-bindings/clock/qcom,sm8550-dispcc.h
+  - include/dt-bindings/clock/qcom,sm8650-dispcc.h
+  - include/dt-bindings/clock/qcom,x1e80100-dispcc.h
 
 properties:
   compatible:
     enum:
       - qcom,sm8550-dispcc
+      - qcom,sm8650-dispcc
+      - qcom,x1e80100-dispcc
 
   clocks:
     items:

Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml

@@ -23,6 +23,7 @@ properties:
       - enum:
           - qcom,sm8550-tcsr
           - qcom,sm8650-tcsr
+          - qcom,x1e80100-tcsr
       - const: syscon
 
   clocks:

Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml

@@ -24,7 +24,9 @@ properties:
     maxItems: 1
 
   clocks:
-    maxItems: 1
+    items:
+      - description: AHB peripheral clock
+      - description: CAN bus clock
 
 required:
   - compatible
@@ -39,7 +41,7 @@ examples:
     can@2010c000 {
         compatible = "microchip,mpfs-can";
         reg = <0x2010c000 0x1000>;
-        clocks = <&clkcfg 17>;
+        clocks = <&clkcfg 17>, <&clkcfg 37>;
         interrupt-parent = <&plic>;
         interrupts = <56>;
     };

Documentation/devicetree/bindings/clock/qcom,sm8650-dispcc.yaml

@@ -418,6 +418,9 @@ static struct clk_core *clk_core_get(struct clk_core *core, u8 p_index)
 	if (IS_ERR(hw))
 		return ERR_CAST(hw);
 
+	if (!hw)
+		return NULL;
+
 	return hw->core;
 }