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petegriffinkrzk
petegriffin
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krzk
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pinctrl: samsung: add dedicated SoC eint suspend/resume callbacks
Refactor the existing platform specific suspend/resume callback so that each SoC variant has it's own callback containing the SoC specific logic. This allows exynosautov920 to have a dedicated function for using eint_con_offset and eint_mask_offset. Also it is easily extendable for gs101 which will need dedicated logic for handling the varying register offset of fltcon0 via eint_fltcon_offset. Reviewed-by: André Draszik <[email protected]> Signed-off-by: Peter Griffin <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
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-85
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3 files changed

+97
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‎drivers/pinctrl/samsung/pinctrl-exynos-arm64.c‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1419,8 +1419,8 @@ static const struct samsung_pin_ctrl exynosautov920_pin_ctrl[] = {
14191419
.pin_banks = exynosautov920_pin_banks0,
14201420
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks0),
14211421
.eint_wkup_init = exynos_eint_wkup_init,
1422-
.suspend = exynos_pinctrl_suspend,
1423-
.resume = exynos_pinctrl_resume,
1422+
.suspend = exynosautov920_pinctrl_suspend,
1423+
.resume = exynosautov920_pinctrl_resume,
14241424
.retention_data = &exynosautov920_retention_data,
14251425
}, {
14261426
/* pin-controller instance 1 AUD data */
@@ -1431,43 +1431,43 @@ static const struct samsung_pin_ctrl exynosautov920_pin_ctrl[] = {
14311431
.pin_banks = exynosautov920_pin_banks2,
14321432
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks2),
14331433
.eint_gpio_init = exynos_eint_gpio_init,
1434-
.suspend = exynos_pinctrl_suspend,
1435-
.resume = exynos_pinctrl_resume,
1434+
.suspend = exynosautov920_pinctrl_suspend,
1435+
.resume = exynosautov920_pinctrl_resume,
14361436
}, {
14371437
/* pin-controller instance 3 HSI1 data */
14381438
.pin_banks = exynosautov920_pin_banks3,
14391439
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks3),
14401440
.eint_gpio_init = exynos_eint_gpio_init,
1441-
.suspend = exynos_pinctrl_suspend,
1442-
.resume = exynos_pinctrl_resume,
1441+
.suspend = exynosautov920_pinctrl_suspend,
1442+
.resume = exynosautov920_pinctrl_resume,
14431443
}, {
14441444
/* pin-controller instance 4 HSI2 data */
14451445
.pin_banks = exynosautov920_pin_banks4,
14461446
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks4),
14471447
.eint_gpio_init = exynos_eint_gpio_init,
1448-
.suspend = exynos_pinctrl_suspend,
1449-
.resume = exynos_pinctrl_resume,
1448+
.suspend = exynosautov920_pinctrl_suspend,
1449+
.resume = exynosautov920_pinctrl_resume,
14501450
}, {
14511451
/* pin-controller instance 5 HSI2UFS data */
14521452
.pin_banks = exynosautov920_pin_banks5,
14531453
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks5),
14541454
.eint_gpio_init = exynos_eint_gpio_init,
1455-
.suspend = exynos_pinctrl_suspend,
1456-
.resume = exynos_pinctrl_resume,
1455+
.suspend = exynosautov920_pinctrl_suspend,
1456+
.resume = exynosautov920_pinctrl_resume,
14571457
}, {
14581458
/* pin-controller instance 6 PERIC0 data */
14591459
.pin_banks = exynosautov920_pin_banks6,
14601460
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks6),
14611461
.eint_gpio_init = exynos_eint_gpio_init,
1462-
.suspend = exynos_pinctrl_suspend,
1463-
.resume = exynos_pinctrl_resume,
1462+
.suspend = exynosautov920_pinctrl_suspend,
1463+
.resume = exynosautov920_pinctrl_resume,
14641464
}, {
14651465
/* pin-controller instance 7 PERIC1 data */
14661466
.pin_banks = exynosautov920_pin_banks7,
14671467
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks7),
14681468
.eint_gpio_init = exynos_eint_gpio_init,
1469-
.suspend = exynos_pinctrl_suspend,
1470-
.resume = exynos_pinctrl_resume,
1469+
.suspend = exynosautov920_pinctrl_suspend,
1470+
.resume = exynosautov920_pinctrl_resume,
14711471
},
14721472
};
14731473

‎drivers/pinctrl/samsung/pinctrl-exynos.c‎

Lines changed: 81 additions & 71 deletions
Original file line numberDiff line numberDiff line change
@@ -762,105 +762,115 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
762762
return 0;
763763
}
764764

765-
static void exynos_pinctrl_suspend_bank(struct samsung_pin_bank *bank)
765+
static void exynos_set_wakeup(struct samsung_pin_bank *bank)
766766
{
767-
struct exynos_eint_gpio_save *save = bank->soc_priv;
768-
const void __iomem *regs = bank->eint_base;
767+
struct exynos_irq_chip *irq_chip;
769768

770-
save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
771-
+ bank->eint_offset);
772-
save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
773-
+ 2 * bank->eint_offset);
774-
save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
775-
+ 2 * bank->eint_offset + 4);
776-
save->eint_mask = readl(regs + bank->irq_chip->eint_mask
777-
+ bank->eint_offset);
778-
779-
pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
780-
pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
781-
pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
782-
pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask);
769+
if (bank->irq_chip) {
770+
irq_chip = bank->irq_chip;
771+
irq_chip->set_eint_wakeup_mask(bank->drvdata, irq_chip);
772+
}
783773
}
784774

785-
static void exynosauto_pinctrl_suspend_bank(struct samsung_pin_bank *bank)
775+
void exynos_pinctrl_suspend(struct samsung_pin_bank *bank)
786776
{
787777
struct exynos_eint_gpio_save *save = bank->soc_priv;
788778
const void __iomem *regs = bank->eint_base;
789779

790-
save->eint_con = readl(regs + bank->pctl_offset + bank->eint_con_offset);
791-
save->eint_mask = readl(regs + bank->pctl_offset + bank->eint_mask_offset);
792-
793-
pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
794-
pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask);
780+
if (bank->eint_type == EINT_TYPE_GPIO) {
781+
save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
782+
+ bank->eint_offset);
783+
save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
784+
+ 2 * bank->eint_offset);
785+
save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
786+
+ 2 * bank->eint_offset + 4);
787+
save->eint_mask = readl(regs + bank->irq_chip->eint_mask
788+
+ bank->eint_offset);
789+
790+
pr_debug("%s: save con %#010x\n",
791+
bank->name, save->eint_con);
792+
pr_debug("%s: save fltcon0 %#010x\n",
793+
bank->name, save->eint_fltcon0);
794+
pr_debug("%s: save fltcon1 %#010x\n",
795+
bank->name, save->eint_fltcon1);
796+
pr_debug("%s: save mask %#010x\n",
797+
bank->name, save->eint_mask);
798+
} else if (bank->eint_type == EINT_TYPE_WKUP) {
799+
exynos_set_wakeup(bank);
800+
}
795801
}
796802

797-
void exynos_pinctrl_suspend(struct samsung_pin_bank *bank)
803+
void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank)
798804
{
799-
struct exynos_irq_chip *irq_chip = NULL;
805+
struct exynos_eint_gpio_save *save = bank->soc_priv;
806+
const void __iomem *regs = bank->eint_base;
800807

801808
if (bank->eint_type == EINT_TYPE_GPIO) {
802-
if (bank->eint_con_offset)
803-
exynosauto_pinctrl_suspend_bank(bank);
804-
else
805-
exynos_pinctrl_suspend_bank(bank);
809+
save->eint_con = readl(regs + bank->pctl_offset +
810+
bank->eint_con_offset);
811+
save->eint_mask = readl(regs + bank->pctl_offset +
812+
bank->eint_mask_offset);
813+
pr_debug("%s: save con %#010x\n",
814+
bank->name, save->eint_con);
815+
pr_debug("%s: save mask %#010x\n",
816+
bank->name, save->eint_mask);
806817
} else if (bank->eint_type == EINT_TYPE_WKUP) {
807-
if (!irq_chip) {
808-
irq_chip = bank->irq_chip;
809-
irq_chip->set_eint_wakeup_mask(bank->drvdata, irq_chip);
810-
}
818+
exynos_set_wakeup(bank);
811819
}
812820
}
813821

814-
static void exynos_pinctrl_resume_bank(struct samsung_pin_bank *bank)
822+
void exynos_pinctrl_resume(struct samsung_pin_bank *bank)
815823
{
816824
struct exynos_eint_gpio_save *save = bank->soc_priv;
817825
void __iomem *regs = bank->eint_base;
818826

819-
pr_debug("%s: con %#010x => %#010x\n", bank->name,
820-
readl(regs + EXYNOS_GPIO_ECON_OFFSET
821-
+ bank->eint_offset), save->eint_con);
822-
pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
823-
readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
824-
+ 2 * bank->eint_offset), save->eint_fltcon0);
825-
pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
826-
readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
827-
+ 2 * bank->eint_offset + 4), save->eint_fltcon1);
828-
pr_debug("%s: mask %#010x => %#010x\n", bank->name,
829-
readl(regs + bank->irq_chip->eint_mask
830-
+ bank->eint_offset), save->eint_mask);
831-
832-
writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
833-
+ bank->eint_offset);
834-
writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
835-
+ 2 * bank->eint_offset);
836-
writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
837-
+ 2 * bank->eint_offset + 4);
838-
writel(save->eint_mask, regs + bank->irq_chip->eint_mask
839-
+ bank->eint_offset);
827+
if (bank->eint_type == EINT_TYPE_GPIO) {
828+
pr_debug("%s: con %#010x => %#010x\n", bank->name,
829+
readl(regs + EXYNOS_GPIO_ECON_OFFSET
830+
+ bank->eint_offset), save->eint_con);
831+
pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
832+
readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
833+
+ 2 * bank->eint_offset), save->eint_fltcon0);
834+
pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
835+
readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
836+
+ 2 * bank->eint_offset + 4),
837+
save->eint_fltcon1);
838+
pr_debug("%s: mask %#010x => %#010x\n", bank->name,
839+
readl(regs + bank->irq_chip->eint_mask
840+
+ bank->eint_offset), save->eint_mask);
841+
842+
writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
843+
+ bank->eint_offset);
844+
writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
845+
+ 2 * bank->eint_offset);
846+
writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
847+
+ 2 * bank->eint_offset + 4);
848+
writel(save->eint_mask, regs + bank->irq_chip->eint_mask
849+
+ bank->eint_offset);
850+
}
840851
}
841852

842-
static void exynosauto_pinctrl_resume_bank(struct samsung_pin_bank *bank)
853+
void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank)
843854
{
844855
struct exynos_eint_gpio_save *save = bank->soc_priv;
845856
void __iomem *regs = bank->eint_base;
846857

847-
pr_debug("%s: con %#010x => %#010x\n", bank->name,
848-
readl(regs + bank->pctl_offset + bank->eint_con_offset), save->eint_con);
849-
pr_debug("%s: mask %#010x => %#010x\n", bank->name,
850-
readl(regs + bank->pctl_offset + bank->eint_mask_offset), save->eint_mask);
851-
852-
writel(save->eint_con, regs + bank->pctl_offset + bank->eint_con_offset);
853-
writel(save->eint_mask, regs + bank->pctl_offset + bank->eint_mask_offset);
854-
855-
}
856-
857-
void exynos_pinctrl_resume(struct samsung_pin_bank *bank)
858-
{
859858
if (bank->eint_type == EINT_TYPE_GPIO) {
860-
if (bank->eint_con_offset)
861-
exynosauto_pinctrl_resume_bank(bank);
862-
else
863-
exynos_pinctrl_resume_bank(bank);
859+
/* exynosautov920 has eint_con_offset for all but one bank */
860+
if (!bank->eint_con_offset)
861+
exynos_pinctrl_resume(bank);
862+
863+
pr_debug("%s: con %#010x => %#010x\n", bank->name,
864+
readl(regs + bank->pctl_offset + bank->eint_con_offset),
865+
save->eint_con);
866+
pr_debug("%s: mask %#010x => %#010x\n", bank->name,
867+
readl(regs + bank->pctl_offset +
868+
bank->eint_mask_offset), save->eint_mask);
869+
870+
writel(save->eint_con,
871+
regs + bank->pctl_offset + bank->eint_con_offset);
872+
writel(save->eint_mask,
873+
regs + bank->pctl_offset + bank->eint_mask_offset);
864874
}
865875
}
866876

‎drivers/pinctrl/samsung/pinctrl-exynos.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -240,6 +240,8 @@ struct exynos_muxed_weint_data {
240240

241241
int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d);
242242
int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d);
243+
void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank);
244+
void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank);
243245
void exynos_pinctrl_suspend(struct samsung_pin_bank *bank);
244246
void exynos_pinctrl_resume(struct samsung_pin_bank *bank);
245247
struct samsung_retention_ctrl *

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