1+ /* verilator lint_off DECLFILENAME */
2+ /* verilator lint_off MULTITOP */
3+
4+ module pyramid_tb ;
5+ parameter Blur0_N = 16 ;
6+ parameter Blur1_N = 16 ;
7+ parameter BlurUp_N = 16 ;
8+ parameter TIMEOUT = 10000 ; // Max cycles before timeout
9+
10+ logic clk, reset;
11+ logic valid_i, ready_i, valid_o, ready_o;
12+ logic [7 : 0 ][7 : 0 ][7 : 0 ] in, out;
13+
14+ // Debug signals
15+ logic [3 : 0 ] st;
16+ logic [1 : 0 ] blur0_st, blur1_st, blur_up_st;
17+ logic [7 : 0 ][7 : 0 ][7 : 0 ] level0_stable;
18+ logic [3 : 0 ][3 : 0 ][7 : 0 ] level1_stable;
19+ logic [7 : 0 ][7 : 0 ][7 : 0 ] upsampled_stable;
20+
21+ // Instantiate the Pyramid module
22+ Pyramid # (
23+ .Blur0_N (Blur0_N),
24+ .Blur1_N (Blur1_N),
25+ .BlurUp_N (BlurUp_N)
26+ ) dut (
27+ .clk (clk),
28+ .reset (reset),
29+ .valid_i (valid_i),
30+ .ready_i (ready_i),
31+ .in (in),
32+ .valid_o (valid_o),
33+ .ready_o (ready_o),
34+ .out (out),
35+ .st (st),
36+ .blur0_st (blur0_st),
37+ .blur1_st (blur1_st),
38+ .blur_up_st (blur_up_st),
39+ .level0_stable (level0_stable),
40+ .level1_stable (level1_stable),
41+ .upsampled_stable (upsampled_stable)
42+ );
43+
44+ // Clock generation
45+ always # 5 clk = ~ clk;
46+
47+ // Simulation control and monitoring
48+ int cycle_count = 0 ;
49+
50+ initial begin
51+ $dumpfile (" pyramid_tb.vcd" );
52+ $dumpvars (0 , pyramid_tb);
53+
54+ // Initialize signals
55+ clk = 0 ;
56+ reset = 1 ;
57+ valid_i = 0 ;
58+ ready_o = 1 ; // Always ready to receive output
59+
60+ // Create a simple test pattern for input
61+ for (int i = 0 ; i < 8 ; i++ ) begin
62+ for (int j = 0 ; j < 8 ; j++ ) begin
63+ in[i][j] = 8 '(i * 8 + j + 1 ); // Pattern: 1,2,3...64
64+ end
65+ end
66+
67+ $display (" === Pyramid Testbench ===" );
68+ $display (" Parameters: Blur0_N=%0d , Blur1_N=%0d , BlurUp_N=%0d " , Blur0_N, Blur1_N, BlurUp_N);
69+ $display (" Input pattern:" );
70+ for (int i = 0 ; i < 8 ; i++ ) begin
71+ $write (" " );
72+ for (int j = 0 ; j < 8 ; j++ ) begin
73+ $write (" %3d " , in[i][j]);
74+ end
75+ $display (" " );
76+ end
77+ $display (" " );
78+
79+ // Reset sequence
80+ repeat (3 ) @ (posedge clk);
81+ reset = 0 ;
82+
83+ // Wait for ready_i
84+ while (! ready_i) begin
85+ @ (posedge clk);
86+ cycle_count++ ;
87+ if (cycle_count > TIMEOUT ) begin
88+ $error (" TIMEOUT: Module never became ready (ready_i)" );
89+ $finish ;
90+ end
91+ end
92+
93+ $display (" Module ready after %0d cycles" , cycle_count);
94+
95+ // Assert valid_i for one cycle
96+ valid_i = 1 ;
97+ @ (posedge clk);
98+ cycle_count++ ;
99+ valid_i = 0 ;
100+
101+ $display (" Input submitted at cycle %0d " , cycle_count);
102+
103+ // Wait for output to be valid
104+ while (! valid_o) begin
105+ @ (posedge clk);
106+ cycle_count++ ;
107+ if (cycle_count > TIMEOUT ) begin
108+ $error (" TIMEOUT: Module never produced output (valid_o) after %0d cycles" , TIMEOUT );
109+ $error (" Final state: st=%0d , blur0_st=%0d , blur1_st=%0d , blur_up_st=%0d " ,
110+ st, blur0_st, blur1_st, blur_up_st);
111+ $finish ;
112+ end
113+
114+ // Progress indicator every 100 cycles
115+ if (cycle_count % 100 == 0 ) begin
116+ $display (" Cycle %0d : st=%0d , blur0_st=%0d , blur1_st=%0d , blur_up_st=%0d " ,
117+ cycle_count, st, blur0_st, blur1_st, blur_up_st);
118+ end
119+ end
120+
121+ $display (" \n === RESULTS ===" );
122+ $display (" Processing completed in %0d cycles" , cycle_count);
123+
124+ $display (" \n Final output:" );
125+ for (int i = 0 ; i < 8 ; i++ ) begin
126+ $write (" " );
127+ for (int j = 0 ; j < 8 ; j++ ) begin
128+ $write (" %3d " , out[i][j]);
129+ end
130+ $display (" " );
131+ end
132+
133+ $display (" \n Debug signals:" );
134+ $display (" Final state: %0d " , st);
135+ $display (" Blur states: blur0=%0d , blur1=%0d , blur_up=%0d " , blur0_st, blur1_st, blur_up_st);
136+
137+ $display (" \n level0_stable (8x8):" );
138+ for (int i = 0 ; i < 8 ; i++ ) begin
139+ $write (" " );
140+ for (int j = 0 ; j < 8 ; j++ ) begin
141+ $write (" %3d " , level0_stable[i][j]);
142+ end
143+ $display (" " );
144+ end
145+
146+ $display (" \n level1_stable (4x4):" );
147+ for (int i = 0 ; i < 4 ; i++ ) begin
148+ $write (" " );
149+ for (int j = 0 ; j < 4 ; j++ ) begin
150+ $write (" %3d " , level1_stable[i][j]);
151+ end
152+ $display (" " );
153+ end
154+
155+ $display (" \n upsampled_stable (8x8):" );
156+ for (int i = 0 ; i < 8 ; i++ ) begin
157+ $write (" " );
158+ for (int j = 0 ; j < 8 ; j++ ) begin
159+ $write (" %3d " , upsampled_stable[i][j]);
160+ end
161+ $display (" " );
162+ end
163+
164+ $display (" \n === TEST COMPLETED SUCCESSFULLY ===" );
165+ $finish ;
166+ end
167+
168+ // Timeout watchdog
169+ initial begin
170+ # (TIMEOUT * 10 ); // 10ns per cycle
171+ $error (" GLOBAL TIMEOUT: Simulation exceeded maximum time" );
172+ $finish ;
173+ end
174+
175+ endmodule
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