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Added avionics PCB :)))#1

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Babyyoda777 wants to merge 6 commits intoavionicsfrom
azlan-avionics
Open

Added avionics PCB :)))#1
Babyyoda777 wants to merge 6 commits intoavionicsfrom
azlan-avionics

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@Babyyoda777
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Fully routed and checked in tolerance with JLCPCB manufacturing capabilities for 4L boards. Schematic needs checking and LCSC parts need assigning.
@AaronDanton
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Only a few minor comments to be fixed

  • Can you run the ERC. This brings up errors about the unused pins on the main chip, it might be worth replacing the labels with unused pin crosses
  • Are you able to put one of the LoRa pins on to the back copper to remove the serpentine, specifically the LoRa pin 15 GPIO 17
  • The DRC also has a few errors, most are from the USB C connector that can be ignored but there is a minor complaint about clearance around VRG_AVDD
  • There is a warning about the BME text not being flipped which might be worth fixing

Other comments:

  • Why 4 layers, and any reason for 2 grounds?

Do you mind also putting the CUSF Logo onto the board and feel free to put your name in the silkscreen. The logo is in the drive (logo-black.svg)

@AaronDanton AaronDanton self-assigned this Feb 8, 2026
@Babyyoda777
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Only a few minor comments to be fixed

  • Can you run the ERC. This brings up errors about the unused pins on the main chip, it might be worth replacing the labels with unused pin crosses
  • Are you able to put one of the LoRa pins on to the back copper to remove the serpentine, specifically the LoRa pin 15 GPIO 17
  • The DRC also has a few errors, most are from the USB C connector that can be ignored but there is a minor complaint about clearance around VRG_AVDD
  • There is a warning about the BME text not being flipped which might be worth fixing

Other comments:

  • Why 4 layers, and any reason for 2 grounds?

Do you mind also putting the CUSF Logo onto the board and feel free to put your name in the silkscreen. The logo is in the drive (logo-black.svg)

Hi, thanks for the review! Will fix the ERC errors soon, I had originally left all the GPIO pins labelled incase we needed to add/remove anything to them. Fixed the serpentine trace as well.

USB-C errors can be ignored, the footprint is well within JLCPCB manufacturing limits. Will fix the text soon too and add the logos!

As for the 4 layers, it's needed for the 50ohm impedance matching required by the LoRa antenna input traces (although it is quite short). 4 layers is also not too much more expensive (maybe $5) and is nice to have.

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