Skip to content

Commit 6ee58c4

Browse files
dansalvatodansalvato
committed
[M68k] Fix incorrect boolean content type (llvm#152572)
M68k's SETCC instruction (`scc`) distinctly fills the destination byte with all 1s. If boolean contents are set to `ZeroOrOneBooleanContent`, LLVM can mistakenly think the destination holds `0x01` instead of `0xff` and emit broken code as a result. This change corrects the boolean content type to `ZeroOrNegativeOneBooleanContent`. For example, this IR: ```llvm define dso_local signext range(i8 0, 2) i8 @testBool(i32 noundef %a) local_unnamed_addr #0 { entry: %cmp = icmp eq i32 %a, 4660 %. = zext i1 %cmp to i8 ret i8 %. } ``` would previously build as: ```asm testBool: ; @testBool cmpi.l llvm#4660, (4,%sp) seq %d0 and.l llvm#255, %d0 rts ``` Notice the `zext` is erroneously not clearing the low bits, and thus the register returns with 255 instead of 1. This patch fixes the issue: ```asm testBool: ; @testBool cmpi.l llvm#4660, (4,%sp) seq %d0 and.l llvm#1, %d0 rts ``` Most of the tests containing `scc` suffered from the same value error as described above, so those tests have been updated to match the new output (which also logically corrects them).
1 parent f608373 commit 6ee58c4

File tree

9 files changed

+170
-105
lines changed

9 files changed

+170
-105
lines changed

‎llvm/lib/Target/M68k/M68kISelLowering.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,9 @@ M68kTargetLowering::M68kTargetLowering(const M68kTargetMachine &TM,
5151

5252
MVT PtrVT = MVT::i32;
5353

54-
setBooleanContents(ZeroOrOneBooleanContent);
54+
// This is based on M68k SetCC (scc) setting the destination byte to all 1s.
55+
// See also getSetCCResultType().
56+
setBooleanContents(ZeroOrNegativeOneBooleanContent);
5557

5658
auto *RegInfo = Subtarget.getRegisterInfo();
5759
setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());

‎llvm/lib/Target/M68k/M68kInstrArithmetic.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -835,7 +835,7 @@ def : Pat<(MxSub 0, i8 :$src), (NEG8d MxDRD8 :$src)>;
835835
def : Pat<(MxSub 0, i16:$src), (NEG16d MxDRD16:$src)>;
836836
def : Pat<(MxSub 0, i32:$src), (NEG32d MxDRD32:$src)>;
837837
// SExt of i1 values.
838-
// Although we specify `ZeroOrOneBooleanContent` for boolean content,
838+
// Although we specify `ZeroOrNegativeOneBooleanContent` for boolean content,
839839
// we're still adding an AND here as we don't know the origin of the i1 value.
840840
def : Pat<(sext_inreg i8:$src, i1), (NEG8d (AND8di MxDRD8:$src, 1))>;
841841
def : Pat<(sext_inreg i16:$src, i1), (NEG16d (AND16di MxDRD16:$src, 1))>;

‎llvm/test/CodeGen/M68k/Arith/add.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -85,9 +85,9 @@ define fastcc i32 @test9(i32 %x, i32 %y) nounwind readnone {
8585
; CHECK: ; %bb.0:
8686
; CHECK-NEXT: sub.l #10, %d0
8787
; CHECK-NEXT: seq %d0
88-
; CHECK-NEXT: and.l #255, %d0
89-
; CHECK-NEXT: sub.l %d0, %d1
90-
; CHECK-NEXT: move.l %d1, %d0
88+
; CHECK-NEXT: ext.w %d0
89+
; CHECK-NEXT: ext.l %d0
90+
; CHECK-NEXT: add.l %d1, %d0
9191
; CHECK-NEXT: rts
9292
%cmp = icmp eq i32 %x, 10
9393
%sub = sext i1 %cmp to i32

‎llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -102,8 +102,9 @@ define fastcc i1 @test2(i32 %v1, i32 %v2) nounwind {
102102
; CHECK-NEXT: suba.l #12, %sp
103103
; CHECK-NEXT: muls.l %d1, %d0
104104
; CHECK-NEXT: svs %d1
105-
; CHECK-NEXT: sub.b #1, %d1
106-
; CHECK-NEXT: bne .LBB4_2
105+
; CHECK-NEXT: and.b #1, %d1
106+
; CHECK-NEXT: cmpi.b #0, %d1
107+
; CHECK-NEXT: beq .LBB4_2
107108
; CHECK-NEXT: ; %bb.1: ; %overflow
108109
; CHECK-NEXT: lea (no,%pc), %a0
109110
; CHECK-NEXT: move.l %a0, (%sp)

‎llvm/test/CodeGen/M68k/Atomics/rmw.ll

Lines changed: 39 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -37,9 +37,10 @@ define i8 @atomicrmw_add_i8(i8 %val, ptr %ptr) {
3737
; ATOMIC-NEXT: move.b %d0, %d3
3838
; ATOMIC-NEXT: sub.b %d2, %d3
3939
; ATOMIC-NEXT: seq %d2
40-
; ATOMIC-NEXT: sub.b #1, %d2
40+
; ATOMIC-NEXT: and.b #1, %d2
41+
; ATOMIC-NEXT: cmpi.b #0, %d2
4142
; ATOMIC-NEXT: move.b %d0, %d2
42-
; ATOMIC-NEXT: bne .LBB0_1
43+
; ATOMIC-NEXT: beq .LBB0_1
4344
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
4445
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
4546
; ATOMIC-NEXT: adda.l #8, %sp
@@ -80,9 +81,10 @@ define i16 @atomicrmw_sub_i16(i16 %val, ptr %ptr) {
8081
; ATOMIC-NEXT: move.w %d0, %d3
8182
; ATOMIC-NEXT: sub.w %d2, %d3
8283
; ATOMIC-NEXT: seq %d2
83-
; ATOMIC-NEXT: sub.b #1, %d2
84+
; ATOMIC-NEXT: and.b #1, %d2
85+
; ATOMIC-NEXT: cmpi.b #0, %d2
8486
; ATOMIC-NEXT: move.w %d0, %d2
85-
; ATOMIC-NEXT: bne .LBB1_1
87+
; ATOMIC-NEXT: beq .LBB1_1
8688
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
8789
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
8890
; ATOMIC-NEXT: adda.l #8, %sp
@@ -121,9 +123,10 @@ define i32 @atomicrmw_and_i32(i32 %val, ptr %ptr) {
121123
; ATOMIC-NEXT: move.l %d0, %d3
122124
; ATOMIC-NEXT: sub.l %d2, %d3
123125
; ATOMIC-NEXT: seq %d2
124-
; ATOMIC-NEXT: sub.b #1, %d2
126+
; ATOMIC-NEXT: and.b #1, %d2
127+
; ATOMIC-NEXT: cmpi.b #0, %d2
125128
; ATOMIC-NEXT: move.l %d0, %d2
126-
; ATOMIC-NEXT: bne .LBB2_1
129+
; ATOMIC-NEXT: beq .LBB2_1
127130
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
128131
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
129132
; ATOMIC-NEXT: adda.l #8, %sp
@@ -194,9 +197,10 @@ define i8 @atomicrmw_or_i8(i8 %val, ptr %ptr) {
194197
; ATOMIC-NEXT: move.b %d0, %d3
195198
; ATOMIC-NEXT: sub.b %d2, %d3
196199
; ATOMIC-NEXT: seq %d2
197-
; ATOMIC-NEXT: sub.b #1, %d2
200+
; ATOMIC-NEXT: and.b #1, %d2
201+
; ATOMIC-NEXT: cmpi.b #0, %d2
198202
; ATOMIC-NEXT: move.b %d0, %d2
199-
; ATOMIC-NEXT: bne .LBB4_1
203+
; ATOMIC-NEXT: beq .LBB4_1
200204
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
201205
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
202206
; ATOMIC-NEXT: adda.l #8, %sp
@@ -242,9 +246,10 @@ define i16 @atmoicrmw_nand_i16(i16 %val, ptr %ptr) {
242246
; ATOMIC-NEXT: move.w %d1, %d3
243247
; ATOMIC-NEXT: sub.w %d2, %d3
244248
; ATOMIC-NEXT: seq %d2
245-
; ATOMIC-NEXT: sub.b #1, %d2
249+
; ATOMIC-NEXT: and.b #1, %d2
250+
; ATOMIC-NEXT: cmpi.b #0, %d2
246251
; ATOMIC-NEXT: move.w %d1, %d2
247-
; ATOMIC-NEXT: bne .LBB5_1
252+
; ATOMIC-NEXT: beq .LBB5_1
248253
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
249254
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
250255
; ATOMIC-NEXT: adda.l #8, %sp
@@ -282,9 +287,10 @@ define i32 @atomicrmw_min_i32(i32 %val, ptr %ptr) {
282287
; ATOMIC-NEXT: move.l %d0, %d3
283288
; ATOMIC-NEXT: sub.l %d2, %d3
284289
; ATOMIC-NEXT: seq %d2
285-
; ATOMIC-NEXT: sub.b #1, %d2
290+
; ATOMIC-NEXT: and.b #1, %d2
291+
; ATOMIC-NEXT: cmpi.b #0, %d2
286292
; ATOMIC-NEXT: move.l %d0, %d2
287-
; ATOMIC-NEXT: beq .LBB6_4
293+
; ATOMIC-NEXT: bne .LBB6_4
288294
; ATOMIC-NEXT: .LBB6_1: ; %atomicrmw.start
289295
; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
290296
; ATOMIC-NEXT: move.l %d2, %d0
@@ -434,9 +440,10 @@ define i8 @atomicrmw_i8_umin(i8 %val, ptr %ptr) {
434440
; ATOMIC-NEXT: move.b %d0, %d3
435441
; ATOMIC-NEXT: sub.b %d2, %d3
436442
; ATOMIC-NEXT: seq %d2
437-
; ATOMIC-NEXT: sub.b #1, %d2
443+
; ATOMIC-NEXT: and.b #1, %d2
444+
; ATOMIC-NEXT: cmpi.b #0, %d2
438445
; ATOMIC-NEXT: move.b %d0, %d2
439-
; ATOMIC-NEXT: beq .LBB8_4
446+
; ATOMIC-NEXT: bne .LBB8_4
440447
; ATOMIC-NEXT: .LBB8_1: ; %atomicrmw.start
441448
; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
442449
; ATOMIC-NEXT: move.b %d2, %d0
@@ -486,9 +493,10 @@ define i16 @atomicrmw_umax_i16(i16 %val, ptr %ptr) {
486493
; ATOMIC-NEXT: move.w %d0, %d3
487494
; ATOMIC-NEXT: sub.w %d2, %d3
488495
; ATOMIC-NEXT: seq %d2
489-
; ATOMIC-NEXT: sub.b #1, %d2
496+
; ATOMIC-NEXT: and.b #1, %d2
497+
; ATOMIC-NEXT: cmpi.b #0, %d2
490498
; ATOMIC-NEXT: move.w %d0, %d2
491-
; ATOMIC-NEXT: beq .LBB9_4
499+
; ATOMIC-NEXT: bne .LBB9_4
492500
; ATOMIC-NEXT: .LBB9_1: ; %atomicrmw.start
493501
; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
494502
; ATOMIC-NEXT: move.w %d2, %d0
@@ -537,9 +545,10 @@ define i16 @atomicrmw_xchg_i16(i16 %val, ptr %ptr) {
537545
; ATOMIC-NEXT: move.w %d0, %d3
538546
; ATOMIC-NEXT: sub.w %d2, %d3
539547
; ATOMIC-NEXT: seq %d2
540-
; ATOMIC-NEXT: sub.b #1, %d2
548+
; ATOMIC-NEXT: and.b #1, %d2
549+
; ATOMIC-NEXT: cmpi.b #0, %d2
541550
; ATOMIC-NEXT: move.w %d0, %d2
542-
; ATOMIC-NEXT: bne .LBB10_1
551+
; ATOMIC-NEXT: beq .LBB10_1
543552
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
544553
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
545554
; ATOMIC-NEXT: adda.l #8, %sp
@@ -577,9 +586,10 @@ define i32 @atomicrmw_xchg_i32(i32 %val, ptr %ptr) {
577586
; ATOMIC-NEXT: move.l %d0, %d3
578587
; ATOMIC-NEXT: sub.l %d2, %d3
579588
; ATOMIC-NEXT: seq %d2
580-
; ATOMIC-NEXT: sub.b #1, %d2
589+
; ATOMIC-NEXT: and.b #1, %d2
590+
; ATOMIC-NEXT: cmpi.b #0, %d2
581591
; ATOMIC-NEXT: move.l %d0, %d2
582-
; ATOMIC-NEXT: bne .LBB11_1
592+
; ATOMIC-NEXT: beq .LBB11_1
583593
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
584594
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
585595
; ATOMIC-NEXT: adda.l #8, %sp
@@ -622,9 +632,10 @@ define i8 @atomicrmw_sub_i8_arid(ptr align 2 %self) {
622632
; ATOMIC-NEXT: move.b %d0, %d2
623633
; ATOMIC-NEXT: sub.b %d1, %d2
624634
; ATOMIC-NEXT: seq %d1
625-
; ATOMIC-NEXT: sub.b #1, %d1
635+
; ATOMIC-NEXT: and.b #1, %d1
636+
; ATOMIC-NEXT: cmpi.b #0, %d1
626637
; ATOMIC-NEXT: move.b %d0, %d1
627-
; ATOMIC-NEXT: bne .LBB12_1
638+
; ATOMIC-NEXT: beq .LBB12_1
628639
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
629640
; ATOMIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
630641
; ATOMIC-NEXT: adda.l #4, %sp
@@ -669,9 +680,10 @@ define i16 @atomicrmw_sub_i16_arid(ptr align 2 %self) {
669680
; ATOMIC-NEXT: move.w %d0, %d2
670681
; ATOMIC-NEXT: sub.w %d1, %d2
671682
; ATOMIC-NEXT: seq %d1
672-
; ATOMIC-NEXT: sub.b #1, %d1
683+
; ATOMIC-NEXT: and.b #1, %d1
684+
; ATOMIC-NEXT: cmpi.b #0, %d1
673685
; ATOMIC-NEXT: move.w %d0, %d1
674-
; ATOMIC-NEXT: bne .LBB13_1
686+
; ATOMIC-NEXT: beq .LBB13_1
675687
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
676688
; ATOMIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
677689
; ATOMIC-NEXT: adda.l #4, %sp
@@ -716,9 +728,10 @@ define i32 @atomicrmw_sub_i32_arid(ptr align 2 %self) {
716728
; ATOMIC-NEXT: move.l %d0, %d2
717729
; ATOMIC-NEXT: sub.l %d1, %d2
718730
; ATOMIC-NEXT: seq %d1
719-
; ATOMIC-NEXT: sub.b #1, %d1
731+
; ATOMIC-NEXT: and.b #1, %d1
732+
; ATOMIC-NEXT: cmpi.b #0, %d1
720733
; ATOMIC-NEXT: move.l %d0, %d1
721-
; ATOMIC-NEXT: bne .LBB14_1
734+
; ATOMIC-NEXT: beq .LBB14_1
722735
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
723736
; ATOMIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
724737
; ATOMIC-NEXT: adda.l #4, %sp

0 commit comments

Comments
 (0)