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mem: Updates for ddr5 and hbm runs #14

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1fc6f9a
mem: added frfcfsGem5 to dramRead state
mbabaie Nov 9, 2021
268a1a4
mem: removed printfs
mbabaie Nov 9, 2021
5bf52e9
mem: latest version of dcache FRFCFS, still testing and debugging
mbabaie Nov 10, 2021
02b42fd
mem: Updates for ddr5 and hbm runs
aakahlow Nov 8, 2021
1fd8e69
mem: remove eval from trafGen script
aakahlow Nov 9, 2021
a6f5b49
mem: added turnaround timing to baseline FRFCFS
mbabaie Nov 11, 2021
ad42e98
mem: Add ddr5-8400 single channel config
aakahlow Nov 13, 2021
b2dae3b
mem: added chooseNext to nvmReadEvent
mbabaie Nov 16, 2021
22c3b7c
mem: first attempt
mbabaie Nov 17, 2021
a99b470
mem: FRFCFS WrBatch PrioritizedDRWr DrainDrWr DrainNvWr
mbabaie Nov 18, 2021
24f6c55
mem: small fix of drainings condition
mbabaie Nov 18, 2021
c4ed0d9
mem: latest version FRFCFS TAT WRBatched Drain,tested Ran and Lin
mbabaie Nov 22, 2021
d87e69f
mem: fixing a typo
mbabaie Nov 23, 2021
7422e22
mem: fixed a bug in write scheduling
mbabaie Nov 23, 2021
fc10f85
mem: Updates for ddr5 and hbm runs
aakahlow Nov 8, 2021
4282df8
mem: remove eval from trafGen script
aakahlow Nov 9, 2021
e0348fe
mem: Add ddr5-8400 single channel config
aakahlow Nov 13, 2021
739f363
mem: small updates in bash scripts (need to compress the command)
aakahlow Nov 23, 2021
2cdc917
mem: HBM 256GB/s interface
aakahlow Dec 3, 2021
b68e720
mem: changes for hbm
aakahlow May 1, 2022
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374 changes: 259 additions & 115 deletions cmds.txt
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111 changes: 111 additions & 0 deletions run_ddr5.sh
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#ddr4_12_1000_WO_Miss

<<<<<<< HEAD
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/1 traffGen.py DDR5_6800_2x8 16MiB 1 linear 1000000000000 128MiB 1000 0 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/2 traffGen.py DDR5_6800_2x8 16MiB 2 linear 1000000000000 128MiB 1000 0 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/4 traffGen.py DDR5_6800_2x8 16MiB 4 linear 1000000000000 128MiB 1000 0 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/8 traffGen.py DDR5_6800_2x8 16MiB 8 linear 1000000000000 128MiB 1000 0 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/16 traffGen.py DDR5_6800_2x8 16MiB 16 linear 1000000000000 128MiB 1000 0 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/32 traffGen.py DDR5_6800_2x8 16MiB 32 linear 1000000000000 128MiB 1000 0 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/64 traffGen.py DDR5_6800_2x8 16MiB 64 linear 1000000000000 128MiB 1000 0 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/128 traffGen.py DDR5_6800_2x8 16MiB 128 linear 1000000000000 128MiB 1000 0 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/256 traffGen.py DDR5_6800_2x8 16MiB 256 linear 1000000000000 128MiB 1000 0 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/512 traffGen.py DDR5_6800_2x8 16MiB 512 linear 1000000000000 128MiB 1000 0 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/1024 traffGen.py DDR5_6800_2x8 16MiB 1024 linear 1000000000000 128MiB 1000 0 NVM_2400_1x64

#ddr4_12_1000_WO_Hit

build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/1 traffGen.py DDR5_6800_2x8 128MiB 1 linear 1000000000000 16MiB 1000 0 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/2 traffGen.py DDR5_6800_2x8 128MiB 2 linear 1000000000000 16MiB 1000 0 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/4 traffGen.py DDR5_6800_2x8 128MiB 4 linear 1000000000000 16MiB 1000 0 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/8 traffGen.py DDR5_6800_2x8 128MiB 8 linear 1000000000000 16MiB 1000 0 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/16 traffGen.py DDR5_6800_2x8 128MiB 16 linear 1000000000000 16MiB 1000 0 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/32 traffGen.py DDR5_6800_2x8 128MiB 32 linear 1000000000000 16MiB 1000 0 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/64 traffGen.py DDR5_6800_2x8 128MiB 64 linear 1000000000000 16MiB 1000 0 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/128 traffGen.py DDR5_6800_2x8 128MiB 128 linear 1000000000000 16MiB 1000 0 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/256 traffGen.py DDR5_6800_2x8 128MiB 256 linear 1000000000000 16MiB 1000 0 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/512 traffGen.py DDR5_6800_2x8 128MiB 512 linear 1000000000000 16MiB 1000 0 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/1024 traffGen.py DDR5_6800_2x8 128MiB 1024 linear 1000000000000 16MiB 1000 0 NVM_2400_1x64

#ddr4_12_1000_RO_Hit

build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/1 traffGen.py DDR5_6800_2x8 128MiB 1 linear 1000000000000 16MiB 1000 100 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/2 traffGen.py DDR5_6800_2x8 128MiB 2 linear 1000000000000 16MiB 1000 100 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/4 traffGen.py DDR5_6800_2x8 128MiB 4 linear 1000000000000 16MiB 1000 100 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/8 traffGen.py DDR5_6800_2x8 128MiB 8 linear 1000000000000 16MiB 1000 100 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/16 traffGen.py DDR5_6800_2x8 128MiB 16 linear 1000000000000 16MiB 1000 100 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/32 traffGen.py DDR5_6800_2x8 128MiB 32 linear 1000000000000 16MiB 1000 100 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/64 traffGen.py DDR5_6800_2x8 128MiB 64 linear 1000000000000 16MiB 1000 100 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/128 traffGen.py DDR5_6800_2x8 128MiB 128 linear 1000000000000 16MiB 1000 100 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/256 traffGen.py DDR5_6800_2x8 128MiB 256 linear 1000000000000 16MiB 1000 100 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/512 traffGen.py DDR5_6800_2x8 128MiB 512 linear 1000000000000 16MiB 1000 100 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/1024 traffGen.py DDR5_6800_2x8 128MiB 1024 linear 1000000000000 16MiB 1000 100 NVM_2400_1x64

#ddr4_12_1000_RO_Miss

build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/1 traffGen.py DDR5_6800_2x8 16MiB 1 linear 1000000000000 128MiB 1000 100 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/2 traffGen.py DDR5_6800_2x8 16MiB 2 linear 1000000000000 128MiB 1000 100 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/4 traffGen.py DDR5_6800_2x8 16MiB 4 linear 1000000000000 128MiB 1000 100 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/8 traffGen.py DDR5_6800_2x8 16MiB 8 linear 1000000000000 128MiB 1000 100 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/16 traffGen.py DDR5_6800_2x8 16MiB 16 linear 1000000000000 128MiB 1000 100 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/32 traffGen.py DDR5_6800_2x8 16MiB 32 linear 1000000000000 128MiB 1000 100 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/64 traffGen.py DDR5_6800_2x8 16MiB 64 linear 1000000000000 128MiB 1000 100 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/128 traffGen.py DDR5_6800_2x8 16MiB 128 linear 1000000000000 128MiB 1000 100 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/256 traffGen.py DDR5_6800_2x8 16MiB 256 linear 1000000000000 128MiB 1000 100 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/512 traffGen.py DDR5_6800_2x8 16MiB 512 linear 1000000000000 128MiB 1000 100 NVM_2400_1x64
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/1024 traffGen.py DDR5_6800_2x8 16MiB 1024 linear 1000000000000 128MiB 1000 100 NVM_2400_1x64
=======
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/1 traffGen.py ddr5_6800 16MiB 1 linear 1000000000000 128MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/2 traffGen.py ddr5_6800 16MiB 2 linear 1000000000000 128MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/4 traffGen.py ddr5_6800 16MiB 4 linear 1000000000000 128MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/8 traffGen.py ddr5_6800 16MiB 8 linear 1000000000000 128MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/16 traffGen.py ddr5_6800 16MiB 16 linear 1000000000000 128MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/32 traffGen.py ddr5_6800 16MiB 32 linear 1000000000000 128MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/64 traffGen.py ddr5_6800 16MiB 64 linear 1000000000000 128MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/128 traffGen.py ddr5_6800 16MiB 128 linear 1000000000000 128MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/256 traffGen.py ddr5_6800 16MiB 256 linear 1000000000000 128MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/512 traffGen.py ddr5_6800 16MiB 512 linear 1000000000000 128MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Miss/1024 traffGen.py ddr5_6800 16MiB 1024 linear 1000000000000 128MiB 1000 0 nvm_2400

#ddr4_12_1000_WO_Hit

build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/1 traffGen.py ddr5_6800 128MiB 1 linear 1000000000000 16MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/2 traffGen.py ddr5_6800 128MiB 2 linear 1000000000000 16MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/4 traffGen.py ddr5_6800 128MiB 4 linear 1000000000000 16MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/8 traffGen.py ddr5_6800 128MiB 8 linear 1000000000000 16MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/16 traffGen.py ddr5_6800 128MiB 16 linear 1000000000000 16MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/32 traffGen.py ddr5_6800 128MiB 32 linear 1000000000000 16MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/64 traffGen.py ddr5_6800 128MiB 64 linear 1000000000000 16MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/128 traffGen.py ddr5_6800 128MiB 128 linear 1000000000000 16MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/256 traffGen.py ddr5_6800 128MiB 256 linear 1000000000000 16MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/512 traffGen.py ddr5_6800 128MiB 512 linear 1000000000000 16MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_WO_Hit/1024 traffGen.py ddr5_6800 128MiB 1024 linear 1000000000000 16MiB 1000 0 nvm_2400

#ddr4_12_1000_RO_Hit

build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/1 traffGen.py ddr5_6800 128MiB 1 linear 1000000000000 16MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/2 traffGen.py ddr5_6800 128MiB 2 linear 1000000000000 16MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/4 traffGen.py ddr5_6800 128MiB 4 linear 1000000000000 16MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/8 traffGen.py ddr5_6800 128MiB 8 linear 1000000000000 16MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/16 traffGen.py ddr5_6800 128MiB 16 linear 1000000000000 16MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/32 traffGen.py ddr5_6800 128MiB 32 linear 1000000000000 16MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/64 traffGen.py ddr5_6800 128MiB 64 linear 1000000000000 16MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/128 traffGen.py ddr5_6800 128MiB 128 linear 1000000000000 16MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/256 traffGen.py ddr5_6800 128MiB 256 linear 1000000000000 16MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/512 traffGen.py ddr5_6800 128MiB 512 linear 1000000000000 16MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Hit/1024 traffGen.py ddr5_6800 128MiB 1024 linear 1000000000000 16MiB 1000 100 nvm_2400

#ddr4_12_1000_RO_Miss

build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/1 traffGen.py ddr5_6800 16MiB 1 linear 1000000000000 128MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/2 traffGen.py ddr5_6800 16MiB 2 linear 1000000000000 128MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/4 traffGen.py ddr5_6800 16MiB 4 linear 1000000000000 128MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/8 traffGen.py ddr5_6800 16MiB 8 linear 1000000000000 128MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/16 traffGen.py ddr5_6800 16MiB 16 linear 1000000000000 128MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/32 traffGen.py ddr5_6800 16MiB 32 linear 1000000000000 128MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/64 traffGen.py ddr5_6800 16MiB 64 linear 1000000000000 128MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/128 traffGen.py ddr5_6800 16MiB 128 linear 1000000000000 128MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/256 traffGen.py ddr5_6800 16MiB 256 linear 1000000000000 128MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/512 traffGen.py ddr5_6800 16MiB 512 linear 1000000000000 128MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_results/ddr5_12_1000_RO_Miss/1024 traffGen.py ddr5_6800 16MiB 1024 linear 1000000000000 128MiB 1000 100 nvm_2400
>>>>>>> 2cdc9177ea24a2f7d3d77c15f25d55d1f5a72704
55 changes: 55 additions & 0 deletions run_ddr5_8400.sh
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#ddr4_12_1000_WO_Miss

build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Miss/1 traffGen.py ddr5_8400 16MiB 1 linear 1000000000000 128MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Miss/2 traffGen.py ddr5_8400 16MiB 2 linear 1000000000000 128MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Miss/4 traffGen.py ddr5_8400 16MiB 4 linear 1000000000000 128MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Miss/8 traffGen.py ddr5_8400 16MiB 8 linear 1000000000000 128MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Miss/16 traffGen.py ddr5_8400 16MiB 16 linear 1000000000000 128MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Miss/32 traffGen.py ddr5_8400 16MiB 32 linear 1000000000000 128MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Miss/64 traffGen.py ddr5_8400 16MiB 64 linear 1000000000000 128MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Miss/128 traffGen.py ddr5_8400 16MiB 128 linear 1000000000000 128MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Miss/256 traffGen.py ddr5_8400 16MiB 256 linear 1000000000000 128MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Miss/512 traffGen.py ddr5_8400 16MiB 512 linear 1000000000000 128MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Miss/1024 traffGen.py ddr5_8400 16MiB 1024 linear 1000000000000 128MiB 1000 0 nvm_2400

#ddr4_12_1000_WO_Hit

build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Hit/1 traffGen.py ddr5_8400 128MiB 1 linear 1000000000000 16MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Hit/2 traffGen.py ddr5_8400 128MiB 2 linear 1000000000000 16MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Hit/4 traffGen.py ddr5_8400 128MiB 4 linear 1000000000000 16MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Hit/8 traffGen.py ddr5_8400 128MiB 8 linear 1000000000000 16MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Hit/16 traffGen.py ddr5_8400 128MiB 16 linear 1000000000000 16MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Hit/32 traffGen.py ddr5_8400 128MiB 32 linear 1000000000000 16MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Hit/64 traffGen.py ddr5_8400 128MiB 64 linear 1000000000000 16MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Hit/128 traffGen.py ddr5_8400 128MiB 128 linear 1000000000000 16MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Hit/256 traffGen.py ddr5_8400 128MiB 256 linear 1000000000000 16MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Hit/512 traffGen.py ddr5_8400 128MiB 512 linear 1000000000000 16MiB 1000 0 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_WO_Hit/1024 traffGen.py ddr5_8400 128MiB 1024 linear 1000000000000 16MiB 1000 0 nvm_2400

#ddr4_12_1000_RO_Hit

build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Hit/1 traffGen.py ddr5_8400 128MiB 1 linear 1000000000000 16MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Hit/2 traffGen.py ddr5_8400 128MiB 2 linear 1000000000000 16MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Hit/4 traffGen.py ddr5_8400 128MiB 4 linear 1000000000000 16MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Hit/8 traffGen.py ddr5_8400 128MiB 8 linear 1000000000000 16MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Hit/16 traffGen.py ddr5_8400 128MiB 16 linear 1000000000000 16MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Hit/32 traffGen.py ddr5_8400 128MiB 32 linear 1000000000000 16MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Hit/64 traffGen.py ddr5_8400 128MiB 64 linear 1000000000000 16MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Hit/128 traffGen.py ddr5_8400 128MiB 128 linear 1000000000000 16MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Hit/256 traffGen.py ddr5_8400 128MiB 256 linear 1000000000000 16MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Hit/512 traffGen.py ddr5_8400 128MiB 512 linear 1000000000000 16MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Hit/1024 traffGen.py ddr5_8400 128MiB 1024 linear 1000000000000 16MiB 1000 100 nvm_2400

#ddr4_12_1000_RO_Miss

build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Miss/1 traffGen.py ddr5_8400 16MiB 1 linear 1000000000000 128MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Miss/2 traffGen.py ddr5_8400 16MiB 2 linear 1000000000000 128MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Miss/4 traffGen.py ddr5_8400 16MiB 4 linear 1000000000000 128MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Miss/8 traffGen.py ddr5_8400 16MiB 8 linear 1000000000000 128MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Miss/16 traffGen.py ddr5_8400 16MiB 16 linear 1000000000000 128MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Miss/32 traffGen.py ddr5_8400 16MiB 32 linear 1000000000000 128MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Miss/64 traffGen.py ddr5_8400 16MiB 64 linear 1000000000000 128MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Miss/128 traffGen.py ddr5_8400 16MiB 128 linear 1000000000000 128MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Miss/256 traffGen.py ddr5_8400 16MiB 256 linear 1000000000000 128MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Miss/512 traffGen.py ddr5_8400 16MiB 512 linear 1000000000000 128MiB 1000 100 nvm_2400
build/X86/gem5.opt --outdir=ddr5_8400_results/ddr5_12_1000_RO_Miss/1024 traffGen.py ddr5_8400 16MiB 1024 linear 1000000000000 128MiB 1000 100 nvm_2400
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