Dram Cache Controller (Hit (rd/wr)+ Miss (rd))

.vscode/settings.json

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+        "strstream": "cpp",
+        "*.tcc": "cpp",
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+        "valarray": "cpp",
+        "variant": "cpp",
+        "bit": "cpp",
+        "shared_mutex": "cpp"
+    }
+}

simple.py

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+from m5.objects import *
+import m5
+
+system = System()
+system.clk_domain = SrcClockDomain()
+system.clk_domain.clock = "4GHz"
+system.clk_domain.voltage_domain = VoltageDomain()
+system.mem_mode = 'timing'
+
+system.generator = PyTrafficGen()
+
+system.mem_ctrl = DcacheCtrl()
+system.mem_ctrl.dram = DDR3_1600_8x8(range=AddrRange('1GB'), in_addr_map=False)
+system.mem_ctrl.nvm = NVM_2400_1x64(range=AddrRange('1GB'))
+
+system.mem_ctrl.dram.tREFI = "1000"
+system.mem_ctrl.orb_max_size = "512"
+system.mem_ctrl.crb_max_size = "32"
+#system.mem_ctrl.static_frontend_latency = "0ns"
+
+system.mem_ranges = [AddrRange('1GB')]
+
+system.generator.port = system.mem_ctrl.port
+
+def createRandomTraffic(tgen):
+    yield tgen.createRandom(100000000000,   # duration
+                            0,          # min_addr
+                            16700000,   # max_adr
+                            64,         # block_size
+                            1000,       # min_period
+                            1000,       # max_period
+                            100,         # rd_perc
+                            0)       # data_limit
+    yield tgen.createExit(0)
+
+def createLinearTraffic(tgen):
+    yield tgen.createLinear(100000000000,   # duration
+                            0,          # min_addr
+                            16700000,   # max_adr
+                            64,         # block_size
+                            1000,       # min_period
+                            1000,       # max_period
+                            100,         # rd_perc
+                            0)          # data_limit
+    yield tgen.createExit(0)
+
+
+root = Root(full_system=False, system=system)
+
+m5.instantiate()
+system.generator.start(createRandomTraffic(system.generator))
+#system.generator.start(createLinearTraffic(system.generator))
+exit_event = m5.simulate()

src/mem/DCMemInterface.py

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+from m5.params import *
+from m5.proxy import *
+
+from m5.objects.AbstractMemory import AbstractMemory
+
+# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
+# channel, rank, bank, row and column, respectively, and going from
+# MSB to LSB.  Available are RoRaBaChCo and RoRaBaCoCh, that are
+# suitable for an open-page policy, optimising for sequential accesses
+# hitting in the open row. For a closed-page policy, RoCoRaBaCh
+# maximises parallelism.
+class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
+
+class DCMemInterface(AbstractMemory):
+    type = 'DCMemInterface'
+    abstract = True
+    cxx_header = "mem/dcmem_interface.hh"
+
+    # Allow the interface to set required controller buffer sizes
+    # each entry corresponds to a burst for the specific memory channel
+    # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
+    # the cacheline size or request/packet size
+    write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
+    read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
+
+    # scheduler, address map
+    addr_mapping = Param.AddrMap('RoRaBaCoCh', "Address mapping policy")
+
+    # size of memory device in Bytes
+    device_size = Param.MemorySize("Size of memory device")
+    # the physical organisation of the memory
+    device_bus_width = Param.Unsigned("data bus width in bits for each "\
+                                      "memory device/chip")
+    burst_length = Param.Unsigned("Burst lenght (BL) in beats")
+    device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\
+                                           "device/chip")
+    devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
+    ranks_per_channel = Param.Unsigned("Number of ranks per channel")
+    banks_per_rank = Param.Unsigned("Number of banks per rank")
+
+    # timing behaviour and constraints - all in nanoseconds
+
+    # the base clock period of the memory
+    tCK = Param.Latency("Clock period")
+
+    # time to complete a burst transfer, typically the burst length
+    # divided by two due to the DDR bus, but by making it a parameter
+    # it is easier to also evaluate SDR memories like WideIO and new
+    # interfaces, emerging technologies.
+    # This parameter has to account for burst length.
+    # Read/Write requests with data size larger than one full burst are broken
+    # down into multiple requests in the controller
+    tBURST = Param.Latency("Burst duration "
+                           "(typically burst length / 2 cycles)")
+
+    # write-to-read, same rank turnaround penalty
+    tWTR = Param.Latency("Write to read, same rank switching time")
+
+    # read-to-write, same rank turnaround penalty
+    tRTW = Param.Latency("Read to write, same rank switching time")
+
+    # rank-to-rank bus delay penalty
+    # this does not correlate to a memory timing parameter and encompasses:
+    # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
+    # different rank bus delay
+    tCS = Param.Latency("Rank to rank switching time")