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67 changes: 67 additions & 0 deletions simple_stats_dump.py
Original file line number Diff line number Diff line change
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from m5.objects import *
import m5

system = System()
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = "4GHz"
system.clk_domain.voltage_domain = VoltageDomain()
system.mem_mode = 'timing'

system.generator = PyTrafficGen()

system.mem_ctrl = DcacheCtrl()
system.mem_ctrl.dram = DDR3_1600_8x8(range=AddrRange('1GB'), in_addr_map=False)
system.mem_ctrl.nvm = NVM_2400_1x64(range=AddrRange('1GB'))

system.mem_ctrl.dram.tREFI = "1000"
system.mem_ctrl.nvm.max_pending_reads = "256"
system.mem_ctrl.orb_max_size = "512"
system.mem_ctrl.crb_max_size = "32"
#system.mem_ctrl.static_frontend_latency = "0ns"

system.mem_ranges = [AddrRange('1GB')]

system.generator.port = system.mem_ctrl.port

def createRandomTraffic(tgen):
yield tgen.createRandom(100000000, # duration 100000000000
0, # min_addr
16700000, # max_adr
64, # block_size
1000, # min_period
1000, # max_period
50, # rd_perc
0) # data_limit
yield tgen.createExit(0)

def createLinearTraffic(tgen):
yield tgen.createLinear(1000000000000, # duration
0, # min_addr
16700000, # max_adr
64, # block_size
1000, # min_period
1000, # max_period
100, # rd_perc
0) # data_limit
yield tgen.createExit(0)


root = Root(full_system=False, system=system)

m5.instantiate()
system.generator.start(createRandomTraffic(system.generator))
#system.generator.start(createLinearTraffic(system.generator))

# stop simulation after a certain number of ticks

# dumping stats every x number of ticks

while True:
exit_event = m5.simulate(200000)
exit_cause = exit_event.getCause()
if exit_cause == 'simulate() limit reached':
m5.stats.dump()
print(exit_cause)
else:
print('Exiting simulation!')
break