Main PR by mbabaie · Pull Request #7 · darchr/dramCacheController

mbabaie · 2021-10-15T13:19:22Z

No description provided.

Change-Id: Iacad811fb48cf65be8cfadab7fdb421ad0c98a6b

Change-Id: I3b782f6d72ef64a96d7a2d3133b745dc99d7a025

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Change-Id: Ic50fab42b25fcd98d32fab5d849e896882f82d02

Change-Id: If79e442f3c562ab0455f1c35146a032524d4ec9b

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

Change-Id: Ie7f78f53c5a20b42ff73c1459aaff551a9de1705

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Change-Id: Ibca7d9c95ccea82959cba988502759fc7ff18db4

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powerjg

It's hard to review the main part of this change since most of the file is copy-pasted. I used a local diff tool to make it a bit easier, and so I have a few comments on the main files. However, most of my comments are going to have to wait until they are unified.

I was able to get through everything but the dcache_ctrl.cc

It's really important to do the unification that I have been pushing for. If you need help figuring out how to do this, I can definitely lend a hand.

powerjg · 2021-10-20T18:13:01Z

simple.py

+in_addr_map=False)
+system.mem_ctrl.nvm = NVM_2400_1x64(range=AddrRange('8GB'))
+
+system.mem_ctrl.dram.tREFI = "200"


We should put it on the to do list to figure out this parameter

powerjg · 2021-10-20T18:13:13Z

simple.py

+system.mem_ctrl.orb_max_size = "512"
+system.mem_ctrl.crb_max_size = "32"
+
+system.mem_ranges = [AddrRange('4GB')]


Why 4GB when the NVM has 8GB?

powerjg · 2021-10-20T18:15:08Z

src/mem/packet.hh

    Packet(const RequestPtr &_req, MemCmd _cmd)
        :  cmd(_cmd), id((PacketId)_req.get()), req(_req),
-           data(nullptr), addr(0), _isSecure(false), size(0),
+           data(nullptr),


Why this change?

powerjg · 2021-10-20T18:25:58Z

src/mem/dcmem_interface.hh

+         * Incremented when a refresh event is started as well
+         * Used to determine when a low-power state can be entered
+         */
+        uint32_t outstandingEvents;


We should seriously consider changing this back to a uint8 and adding an assert that it's <20 or something. I don't think we're exactly using the interface code in a way that's expected, and it worries me some that we're not going to get reasonable results.

powerjg · 2021-10-20T18:27:24Z

src/mem/dcmem_interface.hh

+     */
+    void chooseRead(dccPacketQueue& queue);
+
+    void processReadPkt(dccPacket* pkt);


This is a new function. Why is it needed? What does it do? This needs documentation.

powerjg · 2021-10-20T18:27:46Z

src/mem/dcmem_interface.hh

+    }
+
+    Tick
+    writeRespQueueFront()


Needs documentation

powerjg · 2021-10-20T18:29:57Z

src/mem/dcmem_interface.cc

+    uint64_t deviceCapacity = deviceSize / (1024 * 1024) * devicesPerRank *
+                              ranksPerChannel;
+
+    dramDeviceCapacity = deviceCapacity;


This line is different from the original. What's going on here?

powerjg · 2021-10-20T18:31:38Z

src/mem/dcmem_interface.cc

+            // banks state is closed but haven't transitioned pwrState to IDLE
+            // or have outstanding ACT,RD/WR,Auto-PRE sequence scheduled
+            // should have outstanding precharge or read response event
+            //assert(prechargeEvent.scheduled() ||


Why is it ok to drop this assert? It looks like this should never be hit because whenever you open a page you should always close it later.

powerjg · 2021-10-20T18:34:08Z

src/mem/dcmem_interface.cc

+}
+
+void
+NVMDCInterface::processReadPkt(dccPacket* pkt)


I guess this is the chooseReadFunction above but with a specific packet? Some documentation would be helpful.

If it's just the inner part of the above function, then you should remove that inner part and call this function there.

powerjg · 2021-10-20T18:37:20Z

src/mem/dcmem_interface.cc

+    bool read_rdy =  pkt->isRead() && (ctrl->inReadBusState(false)) &&
+               (pkt->readyTime <= curTick()) && (numReadDataReady > 0);
+    bool write_rdy =  !pkt->isRead() && !ctrl->inReadBusState(false) &&
+                !writeRespQueueFull();


In the original the inReadBusState condition is flipped (it's true, not false). Can you explain this change?

Change-Id: I9ce0296b0861bd0dff21f5fad75f9009490150dd

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Change-Id: I0422f1e6a924c37895e67c109884deee98a05a40

aakahlow and others added 30 commits February 23, 2021 23:03

mem: [wip] a rough sketch of integrated mem controller

1f6ff60

Change-Id: Iacad811fb48cf65be8cfadab7fdb421ad0c98a6b

init files

63af958

added Qs

e982073

mem: not unified interface, dcache ctrl always hit dram cache

4c327c5

Change-Id: I3b782f6d72ef64a96d7a2d3133b745dc99d7a025

mem: not unified interface, dcache ctrl always hit dram cache

d067acf

Change-Id: If38a31c4ba0af68d7b90a8cb2ee99a364b66d561

mem: everything before unifying ctrl and intrfc

ae70805

mem: more fix and updates

a0cad47

Change-Id: Ifbfbf4aff79cbab758a35ec2ba07c19fb0b99d43

mem: more fix and updates

0a903ab

Change-Id: I3d335f8c64a605c24c0136c06087e41779e5ea30

mem: minor fix

6b016e7

Change-Id: Ic50fab42b25fcd98d32fab5d849e896882f82d02

mem: minor fix

d7db7b9

Change-Id: If79e442f3c562ab0455f1c35146a032524d4ec9b

mem: Comments on dram cache controller

14253ff

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

mem: more updates

56e1ad6

Change-Id: Ie7f78f53c5a20b42ff73c1459aaff551a9de1705

mem: more update

e2d5658

Change-Id: Iea35abd1d85d22731b6859940517642420411452

mem: more update for hit only

cfced46

Change-Id: I724a84be596e84327488f485ded727f69e60ced2

mem: more update

1de8cf2

Change-Id: I7812f21e19552aab60e003d57ae1b76fc1bf6769

mem: pull from shasta

805664c

Change-Id: I56d5178272a10f1d811de721c4c19962f4fd2abb

mem: adding responses for hits

b39a4ff

Change-Id: I4bea6ea7b61ad7ca404016e6f584c7a6be61b1f0

mem: adding event handler for initial reads

0979c8d

Change-Id: I888dcda7b7dbbaee6e39dce66245a2913b48817d

mem: more updates

d5256bd

Change-Id: Ib1cc88d8daab2a896b848d41ff622a0f4ea99d1f

mem: fixed the assert failed in the memInterface

cc5f320

Change-Id: Id7a9742a140d9bd8de7f01326ce0181129d902de

mem: read miss implemented

949d4d0

Change-Id: I172c4c4b0b6c1de681de5dcbc2feef571b418689

mem: debugging the read miss cases

0325bcc

Change-Id: Id6a8fb12f05ca7ac3a618a80e7bc51dc6f0b00c0

mem: miss Read Only fixed

66abddc

Change-Id: I0322ce93032f1e1d7ac323350036497f9f34b831

mem: latest version hit and miss read clean

9d5b514

Change-Id: Iaa6f0c0a123080b6cc893e0317e7abc7c111b30d

mem: added rd/wr miss clean

494f78e

Change-Id: I68228d5aa01bda1f22c57794a092190cce62a457

mem: all the cases implemented and debugged

29f1401

Change-Id: I1109c0e2db161e5fd69a278b355c1777f3f11a22

mem: latest version all cases implemented tested for billion pkts

0bc5f1b

Change-Id: I812c6f545206b30eb7890eba0f6fa2282c4caec2

mem: fixed the insert/remove isInWriteQueue

fcf8e03

Change-Id: I87674ed82968c125ef1ee49d7b8be5c4ba3f71c2

mem: updated the FW/Merging checks for nvmWritebackQueue

bccfd8a

Change-Id: I0e62bee5f2324cf5a66dc3a713b2d16e087b9e6a

mem: writeback dcc pkt pointer in ROB is removed

80e07c1

Change-Id: Ic54bbe8affd720d0a80e73fe9272a375d4d6882e

mbabaie and others added 8 commits October 15, 2021 00:48

mem: latest version + fixed wrbacks

5120137

Change-Id: Ibca7d9c95ccea82959cba988502759fc7ff18db4

Delete .vscode directory

6d0ab90

Update simple.py

5260a2b

mem: fixed merging wr, removed nwb Q

1df0a67

mem: fixed the NVM Write State, moved to DRAM Read Resp Ready

2ddf0f8

Change-Id: I23e6670d2838857d001f300355783c3193d52256

mem: updated stats for timing in each state

1148617

Change-Id: I0035689d9e0efb57bf290de3bb534251c45f09be

mem: fixing styling and final touch ups

393ec8c

Change-Id: I620038aaaa3252297cbe4465976cc1c63e2540c2

mem: dramCacheSize is set via devicde size from memInterface

9a7d700

Change-Id: I7af51e2c46da527d4f9b0a6a75787522025c8d2d

powerjg reviewed Oct 20, 2021

View reviewed changes

mbabaie and others added 21 commits October 20, 2021 15:21

mem: fixed a tiny bug about dramCacheSize in the previous commit

d7cd2bd

Change-Id: I9ce0296b0861bd0dff21f5fad75f9009490150dd

mem: deleteing mem-pkts for writebacks to nvm (mem leakage)

0b2ec10

Change-Id: Ia90cb99eb6c944e56b3848d2371eaa1aad5e5a01

mem: fixed the NvmWrBack addresses and added stats

f81d190

Change-Id: I88b1ca25c27e8721ba8325756f5f930a7cad4ec2

mem: fixed the inifinite NVM write queue

c1f3865

Change-Id: Ib2d556830cdabd44268bd805d22c8009638c0580

mem: added more stats

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Change-Id: I79e823b6d76a5e87a903bae20481ee13af4fd877

mem: fixed stats

3129273

Change-Id: I77398c0f700563d269c2aeabe58f3bafe6ea7ff9

mem: fixed stats overflow

096f319

Change-Id: Ic037fb09c1c56a78869108caaadbabfd7d38ec48

mem: fixed and added more stats, fixed schedule times

b1df79b

Change-Id: I20ac210b464025eea4946c4f3548ce39783092f5

mem: fixed memory leakage and some stats naming

5129e39

Change-Id: I6abafa642119727e480f8034fbf514c54693a356

mem: latest version

70221ae

Change-Id: I8693b3a696b92fc3a2577e3c19d9675c4812259c

mem: fixed stats delta calculations

c9555dd

Change-Id: I9e482921f1955a6b5b05ddf4c98d462ebda343d5

mem: fixing max size of Qs stats becoming 0 in long runs

30efcc6

Change-Id: I2b8447a99ef9459e1f15c35b31d7bec892a37244

mem: adding two simple stats for counting cold misses

bf2157d

Change-Id: I4b95d58526bc9cd03d9bebc725244e6e46e5a314

mem: fixed the adr/cache size and tag problem causing always hit

ff181b5

Change-Id: I510ad554b99797d84e99c31d6e33da394c07cbcd

mem: traffic generator file

54a4adf

Change-Id: Idc97a96895069db76f041591a776cf173f778a47

mem: updated traffic generator script

ed7255c

Change-Id: Ibc413241753d671465b62ed36f66aa2ee2da8ede

mem: important fix for WR Only cases clogged in NVRead processing

c01c40e

Change-Id: I64b39747f3e5f23046c15c03c4d5e6ddb705b3a1

Add files via upload

5972708

mem: latest/final version of fcfs

9a34171

Change-Id: I446c31c261810440e6cb3d883ed4ccceb3fff28d

mem: latest/final version of fcfs

9d6ea85

Change-Id: I0422f1e6a924c37895e67c109884deee98a05a40

Update dcache_ctrl.cc

30e692d

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Main PR#7

Main PR#7
mbabaie wants to merge 67 commits intodevelopfrom
dcache_orb

mbabaie commented Oct 15, 2021

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mbabaie commented Oct 15, 2021

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