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feat: ShuffleState and QuarterRound AVX2 and SSE3 and ARM AdvSIMD #159
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Pull Request Overview
This PR introduces .NET Hardware Intrinsics support for optimizing ChaCha20 cryptographic operations with AVX2, SSE3, and ARM AdvSIMD instruction sets. The implementation provides SIMD-accelerated versions of core ChaCha20 operations (ShuffleState and QuarterRound) while maintaining backward compatibility with scalar implementations.
Key changes:
- Added hardware intrinsics support for ChaCha20 core operations with AVX2, SSE3, and ARM AdvSIMD
- Enhanced build and test infrastructure to validate intrinsics across different platforms
- Updated dependencies and improved code style consistency across benchmark files
Reviewed Changes
Copilot reviewed 25 out of 25 changed files in this pull request and generated 4 comments.
Show a summary per file
| File | Description |
|---|---|
| src/NaCl.Core/Base/ChaCha20Base.cs | Core SIMD implementation with hardware intrinsics for ShuffleState and QuarterRound operations |
| src/NaCl.Core/Internal/BitUtils.cs | Added SIMD-optimized rotation utilities for Vector128/256 operations |
| test/NaCl.Core.Benchmarks/ChaCha20IntrinsicsBenchmark.cs | New benchmark class specifically for testing hardware intrinsics performance |
| build.cake | Enhanced build script with platform-specific intrinsics testing |
| test/NaCl.Core.Benchmarks/*.cs | Code style improvements and field naming consistency |
| src/NaCl.Core/Internal/ArrayUtils.cs | Fixed method naming inconsistency |
| test/NaCl.Core.Tests/*.cs | Updated test vectors URL and method visibility |
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Codecov Report❌ Patch coverage is
Additional details and impacted files@@ Coverage Diff @@
## master #159 +/- ##
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- Coverage 99.78% 90.42% -9.36%
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Files 14 14
Lines 455 1201 +746
Branches 57 128 +71
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+ Hits 454 1086 +632
- Misses 1 115 +114 ☔ View full report in Codecov by Sentry. 🚀 New features to boost your workflow:
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First take on .NET Hardware Intrinsics:
ChaCha20Base.ShuffleStateChaCha20Base.QuarterRoundImplemented proper SSE2 and AdvSIMD optimizations for Poly1305:
ComputeMacSse2- Uses SSE2 Vector128 intrinsics for:ComputeMacAdvSimd- Uses ARM AdvSIMD Vector128 intrinsics with the same optimization pattern for ARM64 platforms (like macOS)ComputeMacdispatch to check for SSE2 and AdvSIMD support after AVX2Pending:
Salsa20Base