CIX:Add OEM-specific ACPI OEM_ID check for default domain

arch/arm64/configs/deepin_arm64_desktop_defconfig

@@ -3267,6 +3267,7 @@ CONFIG_SND_VX222=m
 CONFIG_SND_YMFPCI=m
 CONFIG_SND_HDA_INTEL=y
 CONFIG_SND_HDA_PHYTIUM=m
+CONFIG_SND_HDA_CIX_IPBLOQ=m
 CONFIG_SND_HDA_HWDEP=y
 CONFIG_SND_HDA_INPUT_BEEP=y
 CONFIG_SND_HDA_PATCH_LOADER=y
@@ -3310,8 +3311,6 @@ CONFIG_SND_ATMEL_SOC=m
 CONFIG_SND_SOC_CIX=m
 CONFIG_SND_SOC_CDNS_I2S_SC_CIX=m
 CONFIG_SND_SOC_CDNS_I2S_MC_CIX=m
-CONFIG_SND_SOC_IPBLOQ_HDA_CIX=m
-CONFIG_SND_HDACODEC_REALTEK_CIX=m
 CONFIG_SND_DESIGNWARE_I2S=m
 CONFIG_SND_DESIGNWARE_PCM=y
 CONFIG_SND_SOC_FSL_ASRC=m
@@ -3606,7 +3605,7 @@ CONFIG_USBIP_HOST=m
 CONFIG_USBIP_VUDC=m
 CONFIG_USB_CDNS_SUPPORT=y
 CONFIG_USB_CDNS3=y
-CONFIG_USB_CDNSP_CIX=y
+CONFIG_USB_CDNSP_CIX=m
 CONFIG_USB_CDNS3_GADGET=y
 CONFIG_USB_CDNS3_HOST=y
 # CONFIG_USB_CDNS3_PCI_WRAP is not set
@@ -3753,7 +3752,7 @@ CONFIG_TYPEC_RT1719=m
 CONFIG_TYPEC_HD3SS3220=m
 CONFIG_TYPEC_STUSB160X=m
 CONFIG_TYPEC_WUSB3801=m
-CONFIG_TYPEC_RTS5453=y
+CONFIG_TYPEC_RTS5453=m
 CONFIG_TYPEC_MUX_FSA4480=m
 CONFIG_TYPEC_MUX_GPIO_SBU=m
 CONFIG_TYPEC_MUX_PI3USB30532=m

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

@@ -2880,6 +2880,34 @@ static int arm_smmu_dev_disable_feature(struct device *dev,
 	}
 }
 
+/*
+ * Check OEM_ID with a specific OEM provider.
+ */
+#ifdef CONFIG_ACPI
+static bool acpi_check_oem_id(struct device *dev, const char *oem_id)
+{
+	if (oem_id && has_acpi_companion(dev)) {
+		struct acpi_table_header *iort_table;
+
+		acpi_status status = acpi_get_table(ACPI_SIG_IORT, 0, &iort_table);
+
+		if (ACPI_FAILURE(status)) {
+			if (status != AE_NOT_FOUND) {
+				const char *msg = acpi_format_exception(status);
+
+				pr_warn("Failed to get table, %s\n", msg);
+			}
+			return 0;
+		}
+
+		if (!strncmp(iort_table->oem_id, oem_id, 6))
+			return 1;
+
+	}
+	return 0;
+}
+#endif
+
 /*
  * HiSilicon PCIe tune and trace device can be used to trace TLP headers on the
  * PCIe link and save the data to memory by DMA. The hardware is restricted to
@@ -2895,7 +2923,11 @@ static int arm_smmu_def_domain_type(struct device *dev)
 
 		if (IS_HISI_PTT_DEVICE(pdev))
 			return IOMMU_DOMAIN_IDENTITY;
-	}
+	} else {
+			if (acpi_check_oem_id(dev, "CIXTEK"))
+				return IOMMU_DOMAIN_DMA;
+		}
+
 
 	return 0;
 }

drivers/soc/cix/acpi/acpi_resource_lookup.c

@@ -174,8 +174,11 @@ static int reset_lookup_handle(const union acpi_object *obj, void *data)
 
 static int rmem_dev_set_dma(struct device *dev, phys_addr_t base, size_t size)
 {
+dev_err(dev, "==== dev[%s], dev->dma[%s]", dev ? "1": "NULL", dev->dma_mem ? "1": "NULL");
 	if (!dev || dev->dma_mem)
 		return -EINVAL;
+dev_err(dev, "==== memblock_is_region_memory[%d], memblock_is_map_memory[%d]",
+	memblock_is_region_memory(base, size), memblock_is_map_memory(base));
 
 	if (!memblock_is_region_memory(base, size)
 		|| memblock_is_map_memory(base))

drivers/usb/cdns3/Kconfig

@@ -24,7 +24,7 @@ config USB_CDNS3
 	  as module, the module will be called cdns3.ko.
 
 config USB_CDNSP_CIX
-       bool "Cadence USBSSP Dual-Role Controller for Cix platform"
+       tristate "Cadence USBSSP Dual-Role Controller for Cix platform"
        depends on USB_CDNS_SUPPORT
 	   depends on ARM64 || COMPILE_TEST
        help

drivers/usb/cdns3/cdnsp-gadget.c

@@ -2071,3 +2071,4 @@ int cdnsp_gadget_init(struct cdns *cdns)
 
 	return 0;
 }
+EXPORT_SYMBOL(cdnsp_gadget_init);

include/sound/hda_codec.h

@@ -258,6 +258,7 @@ struct hda_codec {
 	unsigned int forced_resume:1; /* forced resume for jack */
 	unsigned int no_stream_clean_at_suspend:1; /* do not clean streams at suspend */
 	unsigned int ctl_dev_id:1; /* old control element id build behaviour */
+	unsigned int reconfig_init_verbs:1; /* need reconfig init verbs when system resume */
 
 #ifdef CONFIG_PM
 	unsigned long power_on_acct;

include/sound/hdaudio.h

@@ -292,6 +292,12 @@ struct hdac_bus {
 	const struct hdac_bus_ops *ops;
 	const struct hdac_ext_bus_ops *ext_ops;
 
+	/* address translation from host to hdac */
+	dma_addr_t (*addr_host_to_hdac)(struct hdac_bus *bus, dma_addr_t addr);
+
+	/* configure init verbs */
+	int (*config_init_verbs)(struct hdac_bus *bus, unsigned int vendor_id);
+
 	/* h/w resources */
 	unsigned long addr;
 	void __iomem *remap_addr;

sound/hda/hdac_controller.c

@@ -43,13 +43,17 @@ static void azx_clear_corbrp(struct hdac_bus *bus)
 void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus)
 {
 	WARN_ON_ONCE(!bus->rb.area);
+	dma_addr_t corb_addr, rirb_addr;
 
 	spin_lock_irq(&bus->reg_lock);
 	/* CORB set up */
 	bus->corb.addr = bus->rb.addr;
 	bus->corb.buf = (__le32 *)bus->rb.area;
-	snd_hdac_chip_writel(bus, CORBLBASE, (u32)bus->corb.addr);
-	snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr));
+	corb_addr = bus->corb.addr;
+	if (bus->addr_host_to_hdac)
+		corb_addr = bus->addr_host_to_hdac(bus, bus->corb.addr);
+	snd_hdac_chip_writel(bus, CORBLBASE, (u32)corb_addr);
+	snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(corb_addr));
 
 	/* set the corb size to 256 entries (ULI requires explicitly) */
 	snd_hdac_chip_writeb(bus, CORBSIZE, 0x02);
@@ -69,8 +73,11 @@ void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus)
 	bus->rirb.buf = (__le32 *)(bus->rb.area + 2048);
 	bus->rirb.wp = bus->rirb.rp = 0;
 	memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds));
-	snd_hdac_chip_writel(bus, RIRBLBASE, (u32)bus->rirb.addr);
-	snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr));
+	rirb_addr = bus->rirb.addr;
+	if (bus->addr_host_to_hdac)
+		rirb_addr = bus->addr_host_to_hdac(bus, bus->rirb.addr);
+	snd_hdac_chip_writel(bus, RIRBLBASE, (u32)rirb_addr);
+	snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(rirb_addr));
 
 	/* set the rirb size to 256 entries (ULI requires explicitly) */
 	snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02);
@@ -552,6 +559,8 @@ static void azx_int_clear(struct hdac_bus *bus)
  */
 bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset)
 {
+	dma_addr_t posbuf_addr;
+
 	if (bus->chip_init)
 		return false;
 
@@ -569,8 +578,12 @@ bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset)
 
 	/* program the position buffer */
 	if (bus->use_posbuf && bus->posbuf.addr) {
-		snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr);
-		snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(bus->posbuf.addr));
+		posbuf_addr = bus->posbuf.addr;
+		if (bus->addr_host_to_hdac)
+			posbuf_addr = bus->addr_host_to_hdac(bus, bus->posbuf.addr);
+
+		snd_hdac_chip_writel(bus, DPLBASE, (u32)posbuf_addr);
+		snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(posbuf_addr));
 	}
 
 	bus->chip_init = true;

sound/hda/hdac_device.c

@@ -50,6 +50,7 @@ int snd_hdac_device_init(struct hdac_device *codec, struct hdac_bus *bus,
 	dev->bus = &snd_hda_bus_type;
 	dev->release = default_release;
 	dev->groups = hdac_dev_attr_groups;
+	dev_set_uevent_suppress(dev, 1);
 	dev_set_name(dev, "%s", name);
 	device_enable_async_suspend(dev);
 

sound/hda/hdac_stream.c

@@ -278,6 +278,7 @@ int snd_hdac_stream_setup(struct hdac_stream *azx_dev)
 {
 	struct hdac_bus *bus = azx_dev->bus;
 	struct snd_pcm_runtime *runtime;
+	dma_addr_t bdl_addr, posbuf_addr;
 	unsigned int val;
 
 	if (azx_dev->substream)
@@ -305,17 +306,24 @@ int snd_hdac_stream_setup(struct hdac_stream *azx_dev)
 	snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
 
 	/* program the BDL address */
+	bdl_addr = azx_dev->bdl.addr;
+	if (bus->addr_host_to_hdac)
+		bdl_addr = bus->addr_host_to_hdac(bus, azx_dev->bdl.addr);
 	/* lower BDL address */
-	snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
+	snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)bdl_addr);
 	/* upper BDL address */
 	snd_hdac_stream_writel(azx_dev, SD_BDLPU,
-			       upper_32_bits(azx_dev->bdl.addr));
+			       upper_32_bits(bdl_addr));
 
 	/* enable the position buffer */
 	if (bus->use_posbuf && bus->posbuf.addr) {
+		posbuf_addr = bus->posbuf.addr;
+		if (bus->addr_host_to_hdac)
+			posbuf_addr = bus->addr_host_to_hdac(bus, bus->posbuf.addr);
+
 		if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))
 			snd_hdac_chip_writel(bus, DPLBASE,
-				(u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);
+				(u32)posbuf_addr| AZX_DPLBASE_ENABLE);
 	}
 
 	/* set the interrupt enable bits in the descriptor control register */
@@ -475,6 +483,9 @@ static int setup_bdle(struct hdac_bus *bus,
 			return -EINVAL;
 
 		addr = snd_sgbuf_get_addr(dmab, ofs);
+		if (bus->addr_host_to_hdac)
+			addr = bus->addr_host_to_hdac(bus, addr);
+
 		/* program the address field of the BDL entry */
 		bdl[0] = cpu_to_le32((u32)addr);
 		bdl[1] = cpu_to_le32(upper_32_bits(addr));

sound/pci/hda/Kconfig

@@ -58,6 +58,19 @@ config SND_HDA_TEGRA
 	  To compile this driver as a module, choose M here: the module
 	  will be called snd-hda-tegra.
 
+config SND_HDA_CIX_IPBLOQ
+	tristate "CIX IPBLOQ HD Audio"
+	select SND_HDA
+	select SND_HDA_ALIGNED_MMIO
+	help
+	  Say Y here to support the HDA controller present in CIX SoCs
+
+	  This options enables support for the HD Audio controller
+	  present in some CIX SoCs.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called snd-hda-cix-ipbloq.
+
 if SND_HDA
 
 config SND_HDA_HWDEP

sound/pci/hda/Makefile

@@ -2,6 +2,7 @@
 snd-hda-intel-objs := hda_intel.o
 snd-hda-tegra-objs := hda_tegra.o
 snd-hda-phytium-objs := hda_phytium.o
+snd-hda-cix-ipbloq-objs := hda_cix_ipbloq.o
 
 snd-hda-codec-y := hda_bind.o hda_codec.o hda_jack.o hda_auto_parser.o hda_sysfs.o
 snd-hda-codec-y += hda_controller.o
@@ -72,3 +73,4 @@ obj-$(CONFIG_SND_HDA_SCODEC_TAS2781_I2C) += snd-hda-scodec-tas2781-i2c.o
 obj-$(CONFIG_SND_HDA_INTEL) += snd-hda-intel.o
 obj-$(CONFIG_SND_HDA_TEGRA) += snd-hda-tegra.o
 obj-$(CONFIG_SND_HDA_PHYTIUM) += snd-hda-phytium.o
+obj-$(CONFIG_SND_HDA_CIX_IPBLOQ) += snd-hda-cix-ipbloq.o