arch-arm: Disassemble DSB inst with CRm operand

This is either a symbolic operand such as "SY" or "NSH", or a 4-bit
immediate.

Change-Id: Id2851ba49441c3dbb02a8348cbf4e9b4fe2869f4

Author: bpfoley

src/arch/arm/insts/misc64.cc

@@ -2654,4 +2654,27 @@ IsbOp64::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
     return ss.str();
 }
 
+std::string
+DsbOp64::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
+{
+    std::stringstream ss;
+    ss << "  " << mnemonic << "   ";
+    switch (imm) {
+        case 1:  ss << "OSHLD"; break;
+        case 2:  ss << "OSHST"; break;
+        case 3:  ss << "OSH";   break;
+        case 5:  ss << "NSHLD"; break;
+        case 6:  ss << "NSHST"; break;
+        case 7:  ss << "NSH";   break;
+        case 9:  ss << "ISHLD"; break;
+        case 10: ss << "ISHST"; break;
+        case 11: ss << "ISH";   break;
+        case 13: ss << "LD";    break;
+        case 14: ss << "ST";    break;
+        case 15: ss << "SY";    break;
+        default: ss << "#" << imm; break;
+    }
+    return ss.str();
+}
+
 } // namespace gem5

src/arch/arm/insts/misc64.hh

@@ -371,6 +371,20 @@ class IsbOp64 : public ArmISA::ArmStaticInst
             Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
+class DsbOp64 : public ArmISA::ArmStaticInst
+{
+  protected:
+    uint64_t imm;
+
+    DsbOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
+            OpClass __opClass, uint64_t _imm) :
+        ArmISA::ArmStaticInst(mnem, _machInst, __opClass), imm(_imm)
+    {}
+
+    std::string generateDisassembly(
+            Addr pc, const loader::SymbolTable *symtab) const override;
+};
+
 } // namespace gem5
 
 #endif

src/arch/arm/isa/formats/aarch64.isa

@@ -399,12 +399,12 @@ namespace Aarch64
                             if (bits(crm, 1, 0) == 0b10) {
                                 switch (bits(crm, 3, 2)) {
                                   case 0x1: // Non-Shareable
-                                    return new Dsb64Local(machInst);
+                                    return new Dsb64Local(machInst, crm);
                                   case 0x0: // OuterShareable
                                   case 0x2: // InnerShareable
                                   case 0x3: // FullSystem
                                     return new Dsb64Shareable(
-                                        machInst, dec.dvmEnabled);
+                                        machInst, crm, dec.dvmEnabled);
                                   default:
                                     GEM5_UNREACHABLE;
                                 }
@@ -416,12 +416,12 @@ namespace Aarch64
                           case 0x4:
                             switch (bits(crm, 3, 2)) {
                               case 0x1: // Non-Shareable
-                                return new Dsb64Local(machInst);
+                                return new Dsb64Local(machInst, crm);
                               case 0x0: // OuterShareable
                               case 0x2: // InnerShareable
                               case 0x3: // FullSystem
                                 return new Dsb64Shareable(
-                                    machInst, dec.dvmEnabled);
+                                    machInst, crm, dec.dvmEnabled);
                               default:
                                 GEM5_UNREACHABLE;
                             }

src/arch/arm/isa/insts/misc64.isa

@@ -194,11 +194,11 @@ let {{
     decoder_output += ImmOp64Constructor.subst(isbIop)
     exec_output += BasicExecute.subst(isbIop)
 
-    dsbLocalIop = ArmInstObjParams("dsb", "Dsb64Local", "ArmStaticInst", "",
+    dsbLocalIop = ArmInstObjParams("dsb", "Dsb64Local", "DsbOp64", "",
                                    ['IsReadBarrier', 'IsWriteBarrier',
                                    'IsSerializeAfter'])
-    header_output += BasicDeclare.subst(dsbLocalIop)
-    decoder_output += BasicConstructor64.subst(dsbLocalIop)
+    header_output += ImmOp64Declare.subst(dsbLocalIop)
+    decoder_output += ImmOp64Constructor.subst(dsbLocalIop)
     exec_output += BasicExecute.subst(dsbLocalIop)
 
     dvmCode = '''
@@ -215,7 +215,7 @@ let {{
             PendingDvm = false;
         }
     '''
-    dsbShareableIop = ArmInstObjParams("dsb", "Dsb64Shareable", "ArmStaticInst",
+    dsbShareableIop = ArmInstObjParams("dsb", "Dsb64Shareable", "DsbOp64",
                                        { "code" : "", "dvm_code" : dvmCode },
                                        ['IsReadBarrier', 'IsWriteBarrier',
                                         'IsSerializeAfter'])

src/arch/arm/isa/templates/misc64.isa

@@ -331,7 +331,7 @@ def template DvmDeclare {{
 
       public:
         /// Constructor.
-        %(class_name)s(ExtMachInst machInst, bool dvm_enabled);
+        %(class_name)s(ExtMachInst machInst, uint64_t imm, bool dvm_enabled);
         Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
         Fault completeAcc(PacketPtr, ExecContext *,
                           trace::InstRecord *) const override;
@@ -368,8 +368,9 @@ def template AtConstructor {{
 }};
 
 def template DvmConstructor {{
-    %(class_name)s::%(class_name)s(ExtMachInst machInst, bool dvm_enabled) :
-        %(base_class)s("%(mnemonic)s", machInst, %(op_class)s),
+    %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t imm,
+                                   bool dvm_enabled) :
+        %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, imm),
         dvmEnabled(dvm_enabled)
     {
         %(set_reg_idx_arr)s;