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lines changed Original file line number Diff line number Diff line change 11vhdltool-config.yaml
2-
2+ .project
3+ .library_mapping.xml
Original file line number Diff line number Diff line change @@ -3,23 +3,23 @@ use ieee.std_logic_1164.all;
33use ieee.numeric_std.all ;
44
55entity vga is
6- port (
7- clk : in std_logic ;
8- rst : in std_logic ;
6+ port (
7+ clk : in std_logic ;
8+ rst : in std_logic ;
99
10- hsync : out std_logic ;
11- vsync : out std_logic ;
10+ hsync : out std_logic ;
11+ vsync : out std_logic ;
1212
13- -- Input colors
14- i_red : in std_logic_vector (1 downto 0 );
15- i_blue : in std_logic_vector (1 downto 0 );
16- i_green : in std_logic_vector (1 downto 0 );
13+ -- Input colors
14+ i_red : in std_logic_vector (1 downto 0 );
15+ i_blue : in std_logic_vector (1 downto 0 );
16+ i_green : in std_logic_vector (1 downto 0 );
1717
18- -- Output colors
19- -- 4 x 4 x 4 yields 64 different colors
20- o_red : out std_logic_vector (1 downto 0 );
21- o_blue : out std_logic_vector (1 downto 0 );
22- o_green : out std_logic_vector (1 downto 0 )
18+ -- Output colors
19+ -- 4 x 4 x 4 yields 64 different colors
20+ o_red : out std_logic_vector (1 downto 0 );
21+ o_blue : out std_logic_vector (1 downto 0 );
22+ o_green : out std_logic_vector (1 downto 0 )
2323 );
2424end entity vga;
2525
Original file line number Diff line number Diff line change @@ -19,6 +19,7 @@ targets:
1919 modelsim:
2020 vlog_options: [-timescale=1ns/1ns]
2121 xsim:
22+ mode: gui
2223 xelab_options: [--debug, all, --timescale, 1ns/1ns]
2324 xsim_options: [--view, vga_tb_behav.wcfg]
2425 toplevel: vga_tb
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