fixed: pixel data now comes from outside block

Author: djcopley

src/vga.vhd

@@ -15,6 +15,9 @@ entity vga is
     i_blue : in std_logic_vector(1 downto 0);
     i_green : in std_logic_vector(1 downto 0);
 
+    -- '1' if ready for pixel else '0'
+    pxl_rdy : out std_logic;
+
     -- Output colors
     -- 4 x 4 x 4 yields 64 different colors
     o_red : out std_logic_vector(1 downto 0);
@@ -40,13 +43,6 @@ architecture RTL of vga is
   constant V_BACK_PORCH : natural := V_SYNC_PULSE + 6;
   constant V_WHOLE_LINE : natural := V_BACK_PORCH + 29;
 
-  -- Data for test
-  constant WHITE_PIXEL : std_logic_vector(5 downto 0) := (others => '1');
-
-  alias R : std_logic_vector(1 downto 0) is WHITE_PIXEL(5 downto 4);
-  alias G : std_logic_vector(1 downto 0) is WHITE_PIXEL(3 downto 2);
-  alias B : std_logic_vector(1 downto 0) is WHITE_PIXEL(1 downto 0);
-
   procedure SyncCount(signal count : inout natural;
                       constant wrap : in natural;
                       constant enable : in boolean;
@@ -104,12 +100,16 @@ begin
         -- To display or not to display
         if h_count < H_VISIBLE_AREA and v_count < V_VISIBLE_AREA then
 
-          o_red <= R;
-          o_green <= G;
-          o_blue <= B;
+          pxl_rdy <= '1';
+
+          o_red <= i_red;
+          o_green <= i_green;
+          o_blue <= i_blue;
 
         else
 
+          pxl_rdy <= '0';
+
           o_red <= (others => '0');
           o_green <= (others => '0');
           o_blue <= (others =>'0');

test/vga_tb.vhd

@@ -15,11 +15,18 @@ architecture rtl of vga_tb is
 
   constant RESET_PERIOD : time := 10 us;
 
+  constant WHITE_PIXEL : std_logic_vector(5 downto 0) := (others => '1');
+  alias R : std_logic_vector(1 downto 0) is WHITE_PIXEL(5 downto 4);
+  alias G : std_logic_vector(1 downto 0) is WHITE_PIXEL(3 downto 2);
+  alias B : std_logic_vector(1 downto 0) is WHITE_PIXEL(1 downto 0);
+
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';
 
   signal hsync, vsync : std_logic;
+  signal pxl_rdy : std_logic;
 
+  signal i_red, i_blue, i_green : std_logic_vector(1 downto 0);
   signal o_red, o_blue, o_green : std_logic_vector(1 downto 0);
 
 begin
@@ -33,9 +40,11 @@ begin
         vsync => vsync,
 
         -- Input colors
-        i_red => (others => '0'),
-        i_blue => (others => '0'),
-        i_green => (others => '0'),
+        i_red => i_red,
+        i_blue => i_blue,
+        i_green => i_green,
+
+        pxl_rdy => pxl_rdy,
 
         -- Output colors
         -- 8 x 8 x 8 yields 512 different colors
@@ -57,5 +66,25 @@ begin
     wait;
   end process;
 
-  end architecture rtl;
+  stim : process
+  begin
+
+    wait until falling_edge(clk);
+    if pxl_rdy='1' then
+      i_red <= R;
+      i_green <= G;
+      i_blue <= B;
+    else
+      i_red <= (others => '0');
+      i_green <= (others => '0');
+      i_blue <= (others => '0');
+    end if;
+  end process;
+
+  kill_sim : process
+  begin
+    wait for 100 ms;
+    assert (false) report "-- SIMULATION COMPLETE --" severity failure;
+  end process;
 
+end architecture rtl;