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Use target reg as temp for comparison result
1 parent e5c6b4c commit 13bc555

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2 files changed

+4
-7
lines changed

2 files changed

+4
-7
lines changed

src/coreclr/jit/codegenriscv64.cpp

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1002,15 +1002,14 @@ void CodeGen::genCodeForIncSaturate(GenTree* tree)
10021002

10031003
GenTree* operand = tree->gtGetOp1();
10041004
assert(!operand->isContained());
1005-
regNumber tempReg = internalRegisters.GetSingle(tree);
10061005
// The src must be a register.
10071006
regNumber operandReg = genConsumeReg(operand);
10081007
emitAttr attr = emitActualTypeSize(tree);
10091008
assert(EA_SIZE(attr) == EA_PTRSIZE);
1010-
assert(tempReg != operandReg);
1009+
noway_assert(targetReg != operandReg); // lifetime of the operand register should have been extended
10111010

1012-
GetEmitter()->emitIns_R_R_I(INS_sltiu, attr, tempReg, operandReg, SIZE_T_MAX); // temp = (operand < max) ? 1 : 0;
1013-
GetEmitter()->emitIns_R_R_I(INS_add, attr, targetReg, operandReg, tempReg); // target = operand + temp;
1011+
GetEmitter()->emitIns_R_R_I(INS_sltiu, attr, targetReg, operandReg, SIZE_T_MAX); // temp = (operand < max) ? 1 : 0;
1012+
GetEmitter()->emitIns_R_R_R(INS_add, attr, targetReg, operandReg, targetReg); // target = operand + temp;
10141013

10151014
genProduceReg(tree);
10161015
}

src/coreclr/jit/lsrariscv64.cpp

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -790,9 +790,7 @@ int LinearScan::BuildNode(GenTree* tree)
790790
case GT_INC_SATURATE:
791791
assert(dstCount == 1);
792792
srcCount = 1;
793-
BuildUse(tree->gtGetOp1());
794-
buildInternalIntRegisterDefForNode(tree);
795-
buildInternalRegisterUses();
793+
setDelayFree(BuildUse(tree->gtGetOp1()));
796794
BuildDef(tree);
797795
break;
798796
} // end switch (tree->OperGet())

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