iCEBreaker UART Video

An FPGA project for the iCEBreaker board that receives image data over UART and displays it on a DVI/HDMI PMOD display using an 800x600 VGA signal.

Features

• UART receiver for streaming pixel data to a framebuffer
• VGA signal generation (800x600) output via DVI PMOD
• Sprite rendering with palette support
• PLL-based clock generation (~40MHz dot clock)

Hardware Requirements

• iCEBreaker FPGA board (iCE40 UP5K)
• BML HDMI 12-bit color PMOD board

Building

Requires the open-source iCE40 FPGA toolchain: yosys, nextpnr, and icestorm.

make        # synthesize and build bitstream
make prog   # program the board via iceprog

License

Based on work by Kevin M. Hubbard / Black Mess Labs, licensed under the CERN Open Hardware Licence v1.2.