Fix: read completion channel if OR=1 didn't responsed correctly if

ALEN>0

Author: dpretet

doc/architecture.md

@@ -172,8 +172,8 @@ to 0 the input signals of an interface, and leave unconnected the outputs.
 
 The core supports outstanding requests, and so manages traffic queues per master,
 this traffic can be:
-- in-order if a set of transactions use the same ID
-- out-of-order if a set of transactions use different IDs
+- in-order if a set of transactions uses the same ID
+- out-of-order if a set of transactions uses different IDs
 
 The core doesn't manipulate IDs to enhance the quality-of-service or perform any optimization, so
 the user can be sure the read or write requests will be issued to the master interface(s) in the

rtl/axicb_slv_ooo.sv

@@ -276,7 +276,7 @@ module axicb_slv_ooo
             .i_ready (pipe_aready),
             .i_data  (pipe_in),
             .o_valid (pipe_valid),
-            .o_ready (c_ready),
+            .o_ready (c_end),
             .o_data  (pipe_out)
         );