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Change: Use AXI_SIGNALING=1 by default for AXI4 top level AXI-CROSSBAR #89: Commit 7d6d2a5 pushed by dpretet
2h 5m 21s main
main
2h 5m 21s
Change: rework a process to pass verilator compilation in simulation AXI-CROSSBAR #88: Commit 7d6ba25 pushed by dpretet
1h 59m 5s v1.1.1
v1.1.1
1h 59m 5s
Change: rework a process to pass verilator compilation in simulation AXI-CROSSBAR #87: Commit 7d6ba25 pushed by dpretet
1h 58m 39s main
main
1h 58m 39s
Add area estimation, but yosys scripts need to be fine-tuned. Not yet… AXI-CROSSBAR #86: Commit 3ebf3df pushed by dpretet
1h 55m 6s v1.1.0
v1.1.0
1h 55m 6s
Add area estimation, but yosys scripts need to be fine-tuned. Not yet… AXI-CROSSBAR #85: Commit 3ebf3df pushed by dpretet
1h 44m 50s main
main
1h 44m 50s
Merge main branch AXI-CROSSBAR #84: Commit 0e8580c pushed by dpretet
1h 48m 53s ordering
ordering
1h 48m 53s
Fix: #20 issue - misrouted write completion AXI-CROSSBAR #83: Commit 89668b4 pushed by dpretet
1h 46m 52s ordering
ordering
1h 46m 52s
Fix: AXI4 misrouted read completion if ALEN>0 was interleaved because AXI-CROSSBAR #82: Commit df225c8 pushed by dpretet
1h 40m 24s ordering
ordering
1h 40m 24s
Fix: read completion channel if OR=1 didn't responsed correctly if AXI-CROSSBAR #81: Commit 361a4a0 pushed by dpretet
1h 49m 58s ordering
ordering
1h 49m 58s
Change: rewrite ordering rules management chapter AXI-CROSSBAR #80: Commit 287a92f pushed by dpretet
1h 7m 48s ordering
ordering
1h 7m 48s
Change: Update documentation to add OoO support mentions AXI-CROSSBAR #79: Commit 640272d pushed by dpretet
1h 22m 26s ordering
ordering
1h 22m 26s
New: add a full support OoO to read channel of slave switch AXI-CROSSBAR #78: Commit 5a4e255 pushed by dpretet
1h 14m 23s ordering
ordering
1h 14m 23s
Change: Split CI synthesis in two AXI4 and AXI4-lite jobs AXI-CROSSBAR #77: Commit 2836a75 pushed by dpretet
1h 37m 19s ordering
ordering
1h 37m 19s
New: Split regression by running AXI4 and AXI4-lite separately AXI-CROSSBAR #76: Commit 755cd38 pushed by dpretet
1h 47m 56s ordering
ordering
1h 47m 56s
Change: Run more traffic on Github CI flow AXI-CROSSBAR #75: Commit 2062647 pushed by dpretet
2h 40m 33s ordering
ordering
2h 40m 33s
Fix: OoO switch didn't correcly manage concurrent completions with di… AXI-CROSSBAR #74: Commit e38a4ed pushed by dpretet
1h 22m 43s ordering
ordering
1h 22m 43s
AXI-CROSSBAR AXI-CROSSBAR #73: by dpretet
1h 14m 47s ordering
ordering
1h 14m 47s
Adjust timeout AXI-CROSSBAR #72: Commit 7f3591c pushed by dpretet
1h 11m 21s ordering
ordering
1h 11m 21s
Adjust timeout AXI-CROSSBAR #71: Commit 0bd8ded pushed by dpretet
11m 18s ordering
ordering
11m 18s
Fix: Ensure WCH FIFO is not full before accepting a new write request… AXI-CROSSBAR #70: Commit 08864d3 pushed by dpretet
8m 50s ordering
ordering
8m 50s
Change: use IP parameters to set the max boundary of a testcase AXI-CROSSBAR #69: Commit 266e7cb pushed by dpretet
13m 31s ordering
ordering
13m 31s
Slight polish of CI scripts AXI-CROSSBAR #68: Commit 9fe540a pushed by dpretet
12m 55s ordering
ordering
12m 55s
Slight polish of CI scripts AXI-CROSSBAR #67: Commit 7aa2dce pushed by dpretet
2m 5s ordering
ordering
2m 5s
Slight polish of CI scripts AXI-CROSSBAR #66: Commit 00a7357 pushed by dpretet
24s ordering
ordering
24s
New: Add new testbench configuration to check OR>1 and routing capabi… AXI-CROSSBAR #65: Commit 479d77c pushed by dpretet
13m 13s ordering
ordering
13m 13s