Fix: AXI4 misrouted read completion if ALEN>0 was interleaved because

round robin was always active
Change: Align and clean rd and wr slave switch codes

Author: dpretet

rtl/axicb_slv_switch_rd.sv

@@ -83,14 +83,12 @@ module axicb_slv_switch_rd
     logic [8         -1:0] a_len;
 
     logic                  rch_en;
-    logic                  rch_en_r;
     logic                  rfirst;
     logic                  rch_mr;
     logic [AXI_ID_W  -1:0] rch_id;
     logic [8         -1:0] rch_len;
     logic [SLV_NB    -1:0] rch_grant;
     logic [8         -1:0] rlen;
-    logic                  rch_running;
     logic                  rch_full;
     logic                  c_end;
 
@@ -144,15 +142,15 @@ module axicb_slv_switch_rd
 
     endgenerate
 
-    assign o_arvalid[0] = (slv_ar_targeted[0]) ? i_arvalid : 1'b0;
-    assign o_arvalid[1] = (slv_ar_targeted[1]) ? i_arvalid : 1'b0;
-    assign o_arvalid[2] = (slv_ar_targeted[2]) ? i_arvalid : 1'b0;
-    assign o_arvalid[3] = (slv_ar_targeted[3]) ? i_arvalid : 1'b0;
+    assign o_arvalid[0] = (slv_ar_targeted[0]) ? i_arvalid & !rch_full : 1'b0;
+    assign o_arvalid[1] = (slv_ar_targeted[1]) ? i_arvalid & !rch_full : 1'b0;
+    assign o_arvalid[2] = (slv_ar_targeted[2]) ? i_arvalid & !rch_full : 1'b0;
+    assign o_arvalid[3] = (slv_ar_targeted[3]) ? i_arvalid & !rch_full : 1'b0;
 
-    assign i_arready = (slv_ar_targeted[0]) ? o_arready[0]:
-                       (slv_ar_targeted[1]) ? o_arready[1]:
-                       (slv_ar_targeted[2]) ? o_arready[2]:
-                       (slv_ar_targeted[3]) ? o_arready[3]:
+    assign i_arready = (slv_ar_targeted[0]) ? o_arready[0] & !rch_full:
+                       (slv_ar_targeted[1]) ? o_arready[1] & !rch_full:
+                       (slv_ar_targeted[2]) ? o_arready[2] & !rch_full:
+                       (slv_ar_targeted[3]) ? o_arready[3] & !rch_full:
                                               ar_misrouting;
 
     assign o_arch = i_arch;
@@ -188,7 +186,7 @@ module axicb_slv_switch_rd
     endgenerate
 
     // OoO ID Management
-    axicb_slv_ooo 
+    axicb_slv_ooo
     #(
         .RD_PATH         (1),
         .AXI_ID_W        (AXI_ID_W),
@@ -197,7 +195,7 @@ module axicb_slv_switch_rd
         .MST_ID_MASK     (MST_ID_MASK),
         .CCH_W           (RCH_W)
     )
-    rresp_ooo 
+    rresp_ooo
     (
         .aclk    (aclk),
         .aresetn (aresetn),
@@ -223,7 +221,7 @@ module axicb_slv_switch_rd
 
     assign c_end = i_rvalid & i_rready & i_rlast;
 
-    // Follow-up rcompletion len for mis-routed traffic 
+    // Follow-up rcompletion len for mis-routed traffic
     // which need to be recreated
     always @ (posedge aclk or negedge aresetn) begin
         if (!aresetn) begin
@@ -256,20 +254,10 @@ module axicb_slv_switch_rd
         end
     end
 
-    
-    always @ (posedge aclk or negedge aresetn) begin
-        if (!aresetn) begin
-            rch_en_r <= '0;
-        end else if (srst) begin
-            rch_en_r <= '0;
-        end else begin
-            if (rch_grant=='0) rch_en_r <= 1'b1;
-            else               rch_en_r <= 1'b0;
-        end
-    end
-
+    // Activates the arbiter in OoO module on first read completion dataphase
+    assign rch_en = rfirst;
 
-    assign rch_en = rfirst | rch_en_r;
+    // Switching logic for RRESP channel
 
     assign i_rvalid = (rch_mr)       ? 1'b1 :
                       (rch_grant[0]) ? o_rvalid[0] :

rtl/axicb_slv_switch_wr.sv

@@ -283,6 +283,8 @@ module axicb_slv_switch_wr
         end
     end
 
+    // TODO: is it really usefull ? round-robin should pass anyway a 
+    // grant value if unmasked value > 0
     assign bch_en = bch_en_c | bch_en_r;
 
     // Switching logic for BRESP channel
@@ -294,10 +296,10 @@ module axicb_slv_switch_wr
                       (bch_grant[3]) ? o_bvalid[3] :
                                        1'b0;
 
-    assign o_bready[0] = bch_grant[0] & i_bready;
-    assign o_bready[1] = bch_grant[1] & i_bready;
-    assign o_bready[2] = bch_grant[2] & i_bready;
-    assign o_bready[3] = bch_grant[3] & i_bready;
+    assign o_bready[0] = bch_grant[0] & i_bready & !bch_mr;
+    assign o_bready[1] = bch_grant[1] & i_bready & !bch_mr;
+    assign o_bready[2] = bch_grant[2] & i_bready & !bch_mr;
+    assign o_bready[3] = bch_grant[3] & i_bready & !bch_mr;
 
     assign i_bch = (bch_mr)        ? {2'h3, bch_id}:
                    (bch_grant[0])  ? o_bch[0*BCH_W+:BCH_W] :