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pre-commit: PR122620 #1958

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cd72015
pre-commit: PR122620
nikic Jan 12, 2025
9171841
pre-commit: Update
github-actions[bot] Jan 12, 2025
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958 changes: 415 additions & 543 deletions bench/abseil-cpp/optimized/bits_test.cc.ll
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759 changes: 377 additions & 382 deletions bench/llvm/optimized/AArch64ISelLowering.cpp.ll
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4 changes: 2 additions & 2 deletions bench/llvm/optimized/AttributorAttributes.cpp.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -68042,7 +68042,7 @@ _ZN4llvm32GetPointerBaseWithConstantOffsetEPNS_5ValueERlRKNS_10DataLayoutEb.exit
124: ; preds = %122
%125 = call noundef range(i32 0, 33) i32 @llvm.cttz.i32(i32 %116, i1 true)
%126 = lshr i32 %117, %125
%127 = call noundef range(i32 0, 33) i32 @llvm.cttz.i32(i32 %120, i1 true)
%127 = zext nneg i8 %115 to i32
%128 = lshr i32 %120, %127
%129 = call i32 @llvm.umin.i32(i32 %125, i32 %127)
%spec.select3334.i.i.i = call i32 @llvm.umin.i32(i32 %126, i32 %128)
Expand Down Expand Up @@ -68795,7 +68795,7 @@ _ZN4llvm32GetPointerBaseWithConstantOffsetEPKNS_5ValueERlRKNS_10DataLayoutEb.exi
215: ; preds = %213
%216 = call noundef range(i32 0, 33) i32 @llvm.cttz.i32(i32 %210, i1 true)
%217 = lshr i32 %211, %216
%218 = call noundef range(i32 0, 33) i32 @llvm.cttz.i32(i32 %189, i1 true)
%218 = zext nneg i8 %.sroa.080.1105.i.i to i32
%219 = lshr i32 %189, %218
%220 = call i32 @llvm.umin.i32(i32 %216, i32 %218)
%spec.select3334.i.i.i = call i32 @llvm.umin.i32(i32 %217, i32 %219)
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97 changes: 44 additions & 53 deletions bench/llvm/optimized/RISCVTargetParser.cpp.ll
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Expand Up @@ -1094,64 +1094,58 @@ _ZN4llvm11raw_ostreamlsEPKc.exit26: ; preds = %77, %75, %71, %69
define dso_local noundef range(i32 0, -7) i32 @_ZN4llvm10RISCVVType15getSEWLMULRatioEjNS_7RISCVII5VLMULE(i32 noundef %0, i8 noundef zeroext %1) local_unnamed_addr #5 {
%3 = zext i8 %1 to i32
%switch.i = icmp ugt i8 %1, 3
%4 = sub nsw i32 8, %3
%5 = lshr i32 8, %4
%6 = shl nuw nsw i32 8, %3
%7 = select i1 %switch.i, i32 %5, i32 %6
%8 = shl i32 %0, 3
%9 = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 %7, i1 true)
%10 = lshr i32 %8, %9
ret i32 %10
%4 = shl i32 %0, 3
%.v = select i1 %switch.i, i32 -5, i32 3
%5 = add nsw i32 %.v, %3
%6 = lshr i32 %4, %5
ret i32 %6
}

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable
define dso_local range(i16 0, 272) i16 @_ZN4llvm10RISCVVType16getSameRatioLMULEjNS_7RISCVII5VLMULEj(i32 noundef %0, i8 noundef zeroext %1, i32 noundef %2) local_unnamed_addr #5 {
%4 = zext i8 %1 to i32
%switch.i.i = icmp ugt i8 %1, 3
%5 = sub nsw i32 8, %4
%6 = lshr i32 8, %5
%7 = shl nuw nsw i32 8, %4
%8 = select i1 %switch.i.i, i32 %6, i32 %7
%9 = shl i32 %0, 3
%10 = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 %8, i1 true)
%11 = lshr i32 %9, %10
%12 = shl i32 %2, 3
%13 = udiv i32 %12, %11
%14 = icmp ugt i32 %13, 7
br i1 %14, label %17, label %15

15: ; preds = %3
%.rhs.trunc = trunc nuw i32 %13 to i8
%16 = udiv i8 8, %.rhs.trunc
%.zext = zext nneg i8 %16 to i32
br label %19

17: ; preds = %3
%18 = lshr i32 %13, 3
br label %19

19: ; preds = %17, %15
%20 = phi i32 [ %.zext, %15 ], [ %18, %17 ]
%21 = tail call range(i32 1, 30) i32 @llvm.ctpop.i32(i32 range(i32 1, 536870912) %20)
%22 = icmp samesign ult i32 %21, 2
%23 = icmp samesign ult i32 %20, 9
%or.cond.i = select i1 %22, i1 %23, i1 false
%24 = icmp ne i32 %20, 1
%25 = or i1 %14, %24
%or.cond = and i1 %25, %or.cond.i
br i1 %or.cond, label %26, label %_ZN4llvm10RISCVVTypeL11isValidLMULEjb.exit.thread

26: ; preds = %19
%27 = tail call noundef range(i32 0, 33) i32 @llvm.ctlz.i32(i32 range(i32 1, 536870912) %20, i1 true)
%28 = xor i32 %27, 31
%29 = sub nuw nsw i32 8, %28
%30 = select i1 %14, i32 %28, i32 %29
%31 = trunc nuw nsw i32 %30 to i16
%5 = shl i32 %0, 3
%.v.i = select i1 %switch.i.i, i32 -5, i32 3
%6 = add nsw i32 %.v.i, %4
%7 = lshr i32 %5, %6
%8 = shl i32 %2, 3
%9 = udiv i32 %8, %7
%10 = icmp ugt i32 %9, 7
br i1 %10, label %13, label %11

11: ; preds = %3
%.rhs.trunc = trunc nuw i32 %9 to i8
%12 = udiv i8 8, %.rhs.trunc
%.zext = zext nneg i8 %12 to i32
br label %15

13: ; preds = %3
%14 = lshr i32 %9, 3
br label %15

15: ; preds = %13, %11
%16 = phi i32 [ %.zext, %11 ], [ %14, %13 ]
%17 = tail call range(i32 1, 30) i32 @llvm.ctpop.i32(i32 range(i32 1, 536870912) %16)
%18 = icmp samesign ult i32 %17, 2
%19 = icmp samesign ult i32 %16, 9
%or.cond.i = select i1 %18, i1 %19, i1 false
%20 = icmp ne i32 %16, 1
%21 = or i1 %10, %20
%or.cond = and i1 %21, %or.cond.i
br i1 %or.cond, label %22, label %_ZN4llvm10RISCVVTypeL11isValidLMULEjb.exit.thread

22: ; preds = %15
%23 = tail call noundef range(i32 0, 33) i32 @llvm.ctlz.i32(i32 range(i32 1, 536870912) %16, i1 true)
%24 = xor i32 %23, 31
%25 = sub nuw nsw i32 8, %24
%26 = select i1 %10, i32 %24, i32 %25
%27 = trunc nuw nsw i32 %26 to i16
br label %_ZN4llvm10RISCVVTypeL11isValidLMULEjb.exit.thread

_ZN4llvm10RISCVVTypeL11isValidLMULEjb.exit.thread: ; preds = %19, %26
%.sroa.0.0 = phi i16 [ %31, %26 ], [ 0, %19 ]
%.sroa.2.0 = phi i16 [ 256, %26 ], [ 0, %19 ]
_ZN4llvm10RISCVVTypeL11isValidLMULEjb.exit.thread: ; preds = %15, %22
%.sroa.0.0 = phi i16 [ %27, %22 ], [ 0, %15 ]
%.sroa.2.0 = phi i16 [ 256, %22 ], [ 0, %15 ]
%.sroa.0.0.insert.insert = or i16 %.sroa.2.0, %.sroa.0.0
ret i16 %.sroa.0.0.insert.insert
}
Expand Down Expand Up @@ -1963,9 +1957,6 @@ declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #15
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #15

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.cttz.i32(i32, i1 immarg) #13

attributes #0 = { mustprogress nofree nounwind willreturn memory(read, inaccessiblemem: none) uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { mustprogress nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { mustprogress nounwind uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
Expand Down
6 changes: 3 additions & 3 deletions bench/llvm/optimized/Value.cpp.ll
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Expand Up @@ -7444,12 +7444,12 @@ _ZN4llvm16dyn_cast_or_nullINS_11ConstantIntENS_8ConstantEEEDaPT0_.exit: ; preds

_ZNK4llvm5APInt11countr_zeroEv.exit: ; preds = %149, %153
%.0.i90 = phi i32 [ %..i91, %149 ], [ %154, %153 ]
%155 = tail call i32 @llvm.umin.i32(i32 %.0.i90, i32 32)
%156 = trunc nuw nsw i32 %155 to i8
%narrow = tail call i32 @llvm.umin.i32(i32 %.0.i90, i32 32)
%155 = trunc nuw nsw i32 %narrow to i8
br label %_ZNK4llvm11Instruction11getMetadataEj.exit.thread

_ZNK4llvm11Instruction11getMetadataEj.exit.thread: ; preds = %78, %_ZNK4llvm8CallBase11getRetAlignEv.exit, %_ZNK4llvm8CallBase17getCalledFunctionEv.exit, %95, %97, %_ZN4llvm16dyn_cast_or_nullINS_8FunctionENS_5ValueEEEDaPT0_.exit.i, %52, %55, %_ZNK4llvm4Type7isSizedEPNS_15SmallPtrSetImplIPS0_EE.exit68, %68, %19, %_ZNK4llvm4Type7isSizedEPNS_15SmallPtrSetImplIPS0_EE.exit, %26, %39, %136, %142, %109, %_ZNK4llvm11Instruction11getMetadataEj.exit, %134, %6, %_ZNK4llvm5APInt11countr_zeroEv.exit, %_ZNK4llvm6MDNode10getOperandEj.exit, %71, %_ZNK4llvm4Type7isSizedEPNS_15SmallPtrSetImplIPS0_EE.exit68.thread, %50, %_ZNK4llvm11GlobalValue27isStrongDefinitionForLinkerEv.exit, %11
%.sroa.0113.0 = phi i8 [ %156, %_ZNK4llvm5APInt11countr_zeroEv.exit ], [ %133, %_ZNK4llvm6MDNode10getOperandEj.exit ], [ %75, %71 ], [ %70, %_ZNK4llvm4Type7isSizedEPNS_15SmallPtrSetImplIPS0_EE.exit68.thread ], [ %.sroa.speculated, %11 ], [ %49, %_ZNK4llvm11GlobalValue27isStrongDefinitionForLinkerEv.exit ], [ %51, %50 ], [ %.sroa.0.0.i.i, %6 ], [ 0, %134 ], [ 0, %_ZNK4llvm11Instruction11getMetadataEj.exit ], [ 0, %109 ], [ 0, %142 ], [ 0, %136 ], [ 0, %39 ], [ 0, %26 ], [ 0, %_ZNK4llvm4Type7isSizedEPNS_15SmallPtrSetImplIPS0_EE.exit ], [ %25, %19 ], [ 0, %68 ], [ 0, %_ZNK4llvm4Type7isSizedEPNS_15SmallPtrSetImplIPS0_EE.exit68 ], [ 0, %55 ], [ %.sroa.096.0.extract.trunc, %52 ], [ %.sroa.0.0.extract.trunc92, %_ZNK4llvm8CallBase11getRetAlignEv.exit ], [ %108, %_ZNK4llvm8CallBase17getCalledFunctionEv.exit ], [ 0, %95 ], [ 0, %97 ], [ 0, %_ZN4llvm16dyn_cast_or_nullINS_8FunctionENS_5ValueEEEDaPT0_.exit.i ], [ 0, %78 ]
%.sroa.0113.0 = phi i8 [ %155, %_ZNK4llvm5APInt11countr_zeroEv.exit ], [ %133, %_ZNK4llvm6MDNode10getOperandEj.exit ], [ %75, %71 ], [ %70, %_ZNK4llvm4Type7isSizedEPNS_15SmallPtrSetImplIPS0_EE.exit68.thread ], [ %.sroa.speculated, %11 ], [ %49, %_ZNK4llvm11GlobalValue27isStrongDefinitionForLinkerEv.exit ], [ %51, %50 ], [ %.sroa.0.0.i.i, %6 ], [ 0, %134 ], [ 0, %_ZNK4llvm11Instruction11getMetadataEj.exit ], [ 0, %109 ], [ 0, %142 ], [ 0, %136 ], [ 0, %39 ], [ 0, %26 ], [ 0, %_ZNK4llvm4Type7isSizedEPNS_15SmallPtrSetImplIPS0_EE.exit ], [ %25, %19 ], [ 0, %68 ], [ 0, %_ZNK4llvm4Type7isSizedEPNS_15SmallPtrSetImplIPS0_EE.exit68 ], [ 0, %55 ], [ %.sroa.096.0.extract.trunc, %52 ], [ %.sroa.0.0.extract.trunc92, %_ZNK4llvm8CallBase11getRetAlignEv.exit ], [ %108, %_ZNK4llvm8CallBase17getCalledFunctionEv.exit ], [ 0, %95 ], [ 0, %97 ], [ 0, %_ZN4llvm16dyn_cast_or_nullINS_8FunctionENS_5ValueEEEDaPT0_.exit.i ], [ 0, %78 ]
ret i8 %.sroa.0113.0
}

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