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pre-commit: PR125501 #2079

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b5bdc19
pre-commit: PR125501
dtcxzyw Feb 3, 2025
6b99622
pre-commit: Update
github-actions[bot] Feb 3, 2025
fe3a082
pre-commit: Remap
github-actions[bot] Feb 3, 2025
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6 changes: 2 additions & 4 deletions bench/coreutils-rs/optimized/56596qkor8w4ma8l.ll
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Expand Up @@ -818,10 +818,8 @@ define hidden void @_ZN5uu_od9prn_float17format_item_flo3217h6de27fb484fc90ebE.l
br i1 %or.cond13.i, label %22, label %14

14: ; preds = %2
%15 = bitcast float %13 to i32
%16 = and i32 %15, 2139095040
%17 = icmp eq i32 %16, 0
br i1 %17, label %_ZN5alloc3fmt6format17h7ead8f60e83381d7E.exit.i, label %22
%15 = tail call i1 @llvm.is.fpclass.f32(float %13, i32 144)
br i1 %15, label %_ZN5alloc3fmt6format17h7ead8f60e83381d7E.exit.i, label %20

_ZN5alloc3fmt6format17h7ead8f60e83381d7E.exit.i: ; preds = %14
call void @llvm.lifetime.start.p0(i64 32, ptr nonnull %7), !noalias !116
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7 changes: 4 additions & 3 deletions bench/hermes/optimized/dtoa.c.ll
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Expand Up @@ -2655,9 +2655,7 @@ if.then940.i: ; preds = %if.end937.i
%243 = load double, ptr %rv.i, align 8
%mul943.i = fmul double %243, 0x3950000000000000
store double %mul943.i, ptr %rv.i, align 8
%244 = bitcast double %mul943.i to i64
%245 = and i64 %244, 9218868437227405312
%tobool946.not.i = icmp eq i64 %245, 0
%244 = call i1 @llvm.is.fpclass.f64(double %mul943.i, i32 240)
br i1 %tobool946.not.i, label %if.then947.i, label %ret.i

if.then947.i: ; preds = %if.then940.i
Expand Down Expand Up @@ -8128,6 +8126,9 @@ declare void @llvm.lifetime.end.p0(i64 immarg, ptr captures(none)) #16
; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.umin.i32(i32, i32) #15

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i1 @llvm.is.fpclass.f64(double, i32 immarg) #15

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: write) uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { nounwind uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #2 = { mustprogress nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
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7 changes: 4 additions & 3 deletions bench/libquic/optimized/dtoa.cc.ll
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Expand Up @@ -2359,9 +2359,7 @@ if.then789: ; preds = %if.end786
%222 = load double, ptr %rv, align 8
%mul792 = fmul double %222, 0x3950000000000000
store double %mul792, ptr %rv, align 8
%223 = bitcast double %mul792 to i64
%224 = and i64 %223, 9218868437227405312
%tobool795.not = icmp eq i64 %224, 0
%223 = tail call i1 @llvm.is.fpclass.f64(double %mul792, i32 240)
br i1 %tobool795.not, label %if.then796, label %ret

if.then796: ; preds = %if.then789
Expand Down Expand Up @@ -5957,6 +5955,9 @@ declare void @llvm.lifetime.start.p0(i64 immarg, ptr captures(none)) #15
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr captures(none)) #15

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i1 @llvm.is.fpclass.f64(double, i32 immarg) #13

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.umin.i32(i32, i32) #13

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36 changes: 12 additions & 24 deletions bench/typst-rs/optimized/2d3c2n5y91mtl0x0.ll
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Expand Up @@ -2876,14 +2876,10 @@ define hidden void @"_ZN136_$LT$palette..alpha..alpha..Alpha$LT$C2$C$T$GT$$u20$a
%.0.i6.i.i = select i1 %5, float %.sroa.5.0.copyload, float %6
%7 = fmul float %.sroa.4.0.copyload, %.0.i6.i.i
%8 = fadd float %.sroa.5.0.copyload, %7
%or.cond1.i.i.i = tail call i1 @llvm.is.fpclass.f32(float %8, i32 408)
%9 = bitcast float %8 to i32
%10 = and i32 %9, 2139095040
%11 = icmp ne i32 %10, 0
%.0.i.i.i.i = and i1 %or.cond1.i.i.i, %11
%12 = fmul float %7, 2.000000e+00
%13 = fdiv float %12, %8
%.0.i.i.i = select i1 %.0.i.i.i.i, float %13, float 0.000000e+00
%or.cond1.i.i.i = tail call i1 @llvm.is.fpclass.f32(float %8, i32 264)
%9 = fmul float %7, 2.000000e+00
%10 = fdiv float %9, %8
%11 = select i1 %or.cond1.i.i.i, float %10, float 0.000000e+00
store float %.sroa.01.0.copyload, ptr %0, align 4
%.sroa.43.0..sroa_idx = getelementptr inbounds nuw i8, ptr %0, i64 4
store float %.0.i.i.i, ptr %.sroa.43.0..sroa_idx, align 4
Expand Down Expand Up @@ -4285,14 +4281,10 @@ define hidden void @"_ZN152_$LT$palette..hsv..Hsv$LT$S$C$T$GT$$u20$as$u20$palett
%6 = load float, ptr %5, align 4, !noundef !7
%7 = fmul float %6, %.0.i6
%8 = fadd float %.val, %7
%or.cond1.i = tail call i1 @llvm.is.fpclass.f32(float %8, i32 408)
%9 = bitcast float %8 to i32
%10 = and i32 %9, 2139095040
%11 = icmp ne i32 %10, 0
%.0.i.i = and i1 %or.cond1.i, %11
%12 = fmul float %7, 2.000000e+00
%13 = fdiv float %12, %8
%.0.i = select i1 %.0.i.i, float %13, float 0.000000e+00
%or.cond1.i = tail call i1 @llvm.is.fpclass.f32(float %8, i32 264)
%9 = fmul float %7, 2.000000e+00
%10 = fdiv float %9, %8
%11 = select i1 %or.cond1.i, float %10, float 0.000000e+00
%.sroa.02.0.copyload = load float, ptr %1, align 4
store float %.sroa.02.0.copyload, ptr %0, align 4
%14 = getelementptr inbounds nuw i8, ptr %0, i64 4
Expand Down Expand Up @@ -31382,14 +31374,10 @@ define hidden void @"_ZN94_$LT$T$u20$as$u20$palette..convert..from_into_color_un
%7 = load float, ptr %6, align 4, !alias.scope !6289, !noalias !6286, !noundef !7
%8 = fmul float %7, %.0.i6.i
%9 = fadd float %.val.i, %8
%or.cond1.i.i = tail call i1 @llvm.is.fpclass.f32(float %9, i32 408)
%10 = bitcast float %9 to i32
%11 = and i32 %10, 2139095040
%12 = icmp ne i32 %11, 0
%.0.i.i.i = and i1 %or.cond1.i.i, %12
%13 = fmul float %8, 2.000000e+00
%14 = fdiv float %13, %9
%.0.i.i = select i1 %.0.i.i.i, float %14, float 0.000000e+00
%or.cond1.i.i = tail call i1 @llvm.is.fpclass.f32(float %9, i32 264)
%10 = fmul float %8, 2.000000e+00
%11 = fdiv float %10, %9
%12 = select i1 %or.cond1.i.i, float %11, float 0.000000e+00
%.sroa.02.0.copyload.i = load float, ptr %1, align 4, !alias.scope !6289, !noalias !6286
store float %.sroa.02.0.copyload.i, ptr %0, align 4, !alias.scope !6286, !noalias !6289
%15 = getelementptr inbounds nuw i8, ptr %0, i64 4
Expand Down
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