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dtcxzyw wants to merge 3 commits into from
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pre-commit: PR134403 #2309

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@dtcxzyw dtcxzyw commented Apr 28, 2025

Link: llvm/llvm-project#134403
Requested by: @dtcxzyw

@github-actions github-actions bot mentioned this pull request Apr 28, 2025
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dtcxzyw commented Apr 28, 2025

Diff mode

runner: ariselab-64c-v2
baseline: llvm/llvm-project@5f704f9
patch: llvm/llvm-project#134403
sha256: b7c2127c580623c10d54bdbe68f6cd39906c10c8c7c38296ee682762c47210ff
commit: 548660c

1610 files changed, 1550362 insertions(+), 1552085 deletions(-)

Improvements:
  memcpyopt.NumStackMove 58517 -> 58628 +0.19%
  correlated-value-propagation.NumDeadCases 68877 -> 68940 +0.09%
  correlated-value-propagation.NumAnd 38152 -> 38159 +0.02%
  sccp.NumDeadBlocks 624301 -> 624404 +0.02%
  correlated-value-propagation.NumNSW 551084 -> 551167 +0.02%
  jump-threading.NumFolds 2219460 -> 2219671 +0.01%
  correlated-value-propagation.NumNNeg 84494 -> 84502 +0.01%
  correlated-value-propagation.NumNUW 513126 -> 513167 +0.01%
  correlated-value-propagation.NumCmps 259262 -> 259281 +0.01%
  correlated-value-propagation.NumAddNSW 238314 -> 238330 +0.01%
Regressions:
  correlated-value-propagation.NumPhis 1111931 -> 1111458 -0.04%
  simplifycfg.NumFoldValueComparisonIntoPredecessors 479117 -> 479071 -0.01%
  jump-threading.NumThreads 2370222 -> 2370026 -0.01%
  memcpyopt.NumCallSlot 589808 -> 589768 -0.01%
  correlated-value-propagation.NumNonNull 8259628 -> 8259145 -0.01%
  instcombine.NumConstProp 122560 -> 122556 -0.00%
  instsimplify.NumSimplified 2175551 -> 2175489 -0.00%
  simplifycfg.NumSinkCommonInstrs 653711 -> 653695 -0.00%
  simplifycfg.NumSinkCommonCode 308007 -> 308000 -0.00%
  gvn.NumGVNSimpl 3957132 -> 3957054 -0.00%

1 1 bench/abseil-cpp/optimized/inlined_vector_test.ll
2 1 bench/actix-rs/optimized/47vbyna8d7p4fmvu.ll
6 9 bench/actix-rs/optimized/xcr5yeosl21p44j.ll
2 2 bench/clap-rs/optimized/3n9sdy3q5n8p0ad5.ll
8 8 bench/clap-rs/optimized/5651dp9k16h53y8x.ll
11 17 bench/coreutils-rs/optimized/qcad8r5ga44hvbl.ll
6 12 bench/diesel-rs/optimized/1k9itxwmy6phzvjw.ll
24 48 bench/diesel-rs/optimized/1mpore8avqzhq9r4.ll
4 7 bench/diesel-rs/optimized/2nqojkvzec127ieh.ll
3 6 bench/diesel-rs/optimized/4l61q7h3mw8r4045.ll
5 8 bench/diesel-rs/optimized/vl08vh3jfmwhanx.ll
84 83 bench/html5ever-rs/optimized/38n20yzo26sy51uu.ll
13 13 bench/image-rs/optimized/1clnprdgqfw2q9lq.ll
6 6 bench/image-rs/optimized/249ukonr3l56u09i.ll
5 5 bench/image-rs/optimized/2s4mh02dvph60euq.ll
3 3 bench/image-rs/optimized/5oy2v8fghrh79s8.ll
9 9 bench/image-rs/optimized/8143hfqbwzfmz2f.ll
26 26 bench/just-rs/optimized/23nlf67cmm9na4ci.ll
4 4 bench/just-rs/optimized/2sblcsgax6v4zfcc.ll
52 50 bench/linux/optimized/reboot.ll
16 16 bench/llvm/optimized/CGExpr.ll
38 41 bench/ockam-rs/optimized/23pvw3nj6m0p9wnd.ll
17 18 bench/rust-analyzer-rs/optimized/1opoiu8yzxku2bb7.ll
92 91 bench/rust-analyzer-rs/optimized/1siyoufv1amkefl9.ll
50 38 bench/rust-analyzer-rs/optimized/3j0nbdwupb3iwt86.ll
58 57 bench/rust-analyzer-rs/optimized/4mnb5su7whazh2aj.ll
7 10 bench/rust-analyzer-rs/optimized/c249cixj978zg74.ll
14 14 bench/rustfmt-rs/optimized/1mznjg1e09hdetpr.ll
7 7 bench/rustfmt-rs/optimized/2iek5i6kf8wd1vt9.ll
34 34 bench/rustfmt-rs/optimized/3sx1t619hmuq0zz7.ll
10 10 bench/rustfmt-rs/optimized/4ns0rlx88oaf4rkk.ll
9 9 bench/rustfmt-rs/optimized/5genfix4t5066ss.ll
15 15 bench/rustfmt-rs/optimized/x2cb3fifm47d4t5.ll
25 25 bench/syn/optimized/19z3k5eqgbxjiezn.ll
22 22 bench/syn/optimized/1isw8n6q6q0tgdaq.ll
14 17 bench/syn/optimized/ofvfd67uyaewjlc.ll
74 73 bench/tokenizers-rs/optimized/10h1ju7dwsvagf79.ll
12 12 bench/tokenizers-rs/optimized/2mot01sr7ebui81b.ll
65 64 bench/tree-sitter-rs/optimized/4pzbn5o6oxp3emp4.ll
47 47 bench/turborepo-rs/optimized/eyin3u3cupdp2wcinr2t4x92g.ll
22 30 bench/typst-rs/optimized/1ru1rhojhbz2vfey.ll
50 61 bench/typst-rs/optimized/3dimj4rf5dyrieyi.ll
8 11 bench/typst-rs/optimized/4qskctz4kwc33g7b.ll
78 77 bench/wasmtime-rs/optimized/1g9fzsxu6f987i7p.ll
4 2 bench/wasmtime-rs/optimized/322yw2dra6hhv794.ll
6 4 bench/wasmtime-rs/optimized/3kgdlzjlx2p3jthq.ll
5 4 bench/wasmtime-rs/optimized/3w5lei6xclrfo3sz.ll
8 4 bench/wasmtime-rs/optimized/4nkh38vfk0kb3m00.ll
15 21 bench/zed-rs/optimized/4s3i3gpn7nuv3jdpoq0skrhno.ll
76 79 bench/zed-rs/optimized/6r72qkitrvbw1ftdc9j10udqo.ll
51 60 bench/zed-rs/optimized/6t4g10gl152q55lxtcl2heeia.ll
48 66 bench/zed-rs/optimized/7almbq0vtpgp7q0c9d6k1td97.ll
10 13 bench/zed-rs/optimized/9awmqr28bdho83r0fgrej0t00.ll
75 87 bench/zed-rs/optimized/9iau01omm5rr9yzc2t1pdns1t.ll
67 70 bench/zed-rs/optimized/b0jacrvunbgse6y69p1vx4gkq.ll
26 29 bench/zed-rs/optimized/eb0f70f7qg0lwhfftqxruwlu9.ll
36 42 bench/zed-rs/optimized/epuo8yz105556scsed5wrqb4z.ll

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github-actions bot commented Apr 28, 2025

Summary of Changes

  1. Addition of Metadata Annotations (!range, !noundef):

    • Multiple instances of load instructions now include additional metadata annotations such as !range and !noundef. For example, in the actix-rs benchmark, we see changes like: 
      %.pr = load i64, ptr %2, align 8, !range !35, !alias.scope !267, !noalias !270, !noundef !11
      This indicates that the loaded value is guaranteed to be within a specific range (defined by !35) and is not undefined (!noundef). These annotations can help LLVM's optimizer make stronger assumptions about the values being loaded.

  2. Modification of Unreachable Block Preds:

    • The preds (predecessors) of several unreachable blocks have been updated to include additional predecessor labels. For instance: 
      default.unreachable: ; preds = %"_ZN6diesel13query_builder8ast_pass17AstPass$LT$DB$GT$8push_sql17h2c5939a20ea34722E.exit", %23
      This change allows for more precise control flow analysis, potentially enabling better optimizations or error reporting.

  3. Adjustments to Switch Instructions:

    • Several switch instructions have been modified to use a new label for the default case (default.unreachable instead of a numbered label). For example: 
      switch i64 %.val.pr.i.i, label %default.unreachable [
      This centralizes the handling of unexpected cases, improving code readability and maintainability.

  4. Updates to Metadata Definitions:

    • Numerous metadata definitions have been altered or added. For example: 
      !2161 = !{i8 0, i8 14}
      These updates provide more detailed information about the arguments and their expected ranges or properties, aiding LLVM's alias analysis and other optimizations.

  5. Improved Alias Analysis Annotations:

    • Many load and store instructions now include refined alias analysis metadata. For example: 
      store i64 %.sroa.020.0.copyload.i.i, ptr %.sroa.410.0..sroa_idx.i.i, align 8, !alias.scope !3770, !noalias !3771
      These annotations help LLVM's optimizer understand memory access patterns better, leading to potential improvements in memory-related optimizations.

High-Level Overview

The changes primarily focus on enhancing the metadata associated with various instructions in the LLVM IR. Specifically, the introduction of !range and !noundef annotations provides the optimizer with stronger guarantees about the values being loaded, enabling it to perform more aggressive optimizations. Additionally, adjustments to the predecessors of unreachable blocks and the default labels in switch instructions improve control flow analysis. The modifications to metadata definitions further refine the information available to LLVM's optimization passes, particularly regarding alias analysis and argument properties. These changes collectively aim to improve the efficiency and correctness of the generated machine code by providing the compiler with more precise information about the program's behavior.

model: qwen-plus-latest
CompletionUsage(completion_tokens=715, prompt_tokens=110136, total_tokens=110851, completion_tokens_details=None, prompt_tokens_details=None)

@dtcxzyw dtcxzyw closed this Apr 28, 2025
@dtcxzyw dtcxzyw deleted the test-run14705111157 branch May 18, 2025 09:31
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