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pre-commit: PR150420 #2610

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e53981d
pre-commit: PR150420
dtcxzyw Jul 26, 2025
f905933
pre-commit: Update
github-actions[bot] Jul 26, 2025
b3dc255
pre-commit: Remap
github-actions[bot] Jul 26, 2025
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6 changes: 2 additions & 4 deletions bench/abc/optimized/cmdUtils.ll
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Expand Up @@ -418,10 +418,8 @@ define ptr @CmdSplitLine(ptr noundef readonly captures(none) %0, ptr noundef %1,
br label %.preheader76, !llvm.loop !51

37: ; preds = %.preheader76, %28
%.058.lcssa = phi i32 [ %.058, %.preheader76 ], [ 0, %28 ]
%.0.lcssa = phi i32 [ %.0, %.preheader76 ], [ 0, %28 ]
%38 = icmp ne i32 %.058.lcssa, 0
%39 = icmp ne i32 %.0.lcssa, 0
%38 = icmp ne i32 %.058, 0
%39 = icmp ne i32 %.0, 0
%or.cond6 = select i1 %38, i1 true, i1 %39
br i1 %or.cond6, label %40, label %43

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64 changes: 34 additions & 30 deletions bench/abc/optimized/nwkSpeedup.ll
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Expand Up @@ -836,39 +836,43 @@ define ptr @Nwk_ManSpeedup(ptr noundef %0, i32 noundef %1, i32 noundef %2, i32 n
%exitcond.not = icmp eq i64 %indvars.iv.next452, %wide.trip.count
br i1 %exitcond.not, label %.critedge4, label %71, !llvm.loop !75

.critedge4: ; preds = %71, %82, %.preheader400
%.1237.lcssa = phi i32 [ %.0236413, %.preheader400 ], [ %.2238, %82 ], [ %.1237407, %71 ]
%83 = getelementptr inbounds nuw i8, ptr %61, i64 36
%84 = load i32, ptr %83, align 4, !tbaa !73
%85 = sext i32 %84 to i64
%86 = getelementptr inbounds i32, ptr %calloc, i64 %85
%87 = load i32, ptr %86, align 4, !tbaa !68
%88 = and i32 %87, 1431655765
%89 = lshr i32 %87, 1
%90 = and i32 %89, 1431655765
%91 = add nuw i32 %90, %88
%92 = and i32 %91, 858993459
%93 = lshr i32 %91, 2
%94 = and i32 %93, 858993459
%95 = add nuw nsw i32 %94, %92
%96 = and i32 %95, 117901063
%97 = lshr i32 %95, 4
%98 = and i32 %97, 117901063
%99 = add nuw nsw i32 %98, %96
%100 = and i32 %99, 983055
%101 = lshr i32 %99, 8
%102 = and i32 %101, 983055
%103 = add nuw nsw i32 %102, %100
%104 = and i32 %103, 31
%105 = lshr i32 %103, 16
%106 = add i32 %105, %.0234414
%107 = add i32 %106, %104
%108 = freeze i32 %.1237.lcssa
.critedge4: ; preds = %82, %71
%.1237.lcssa = phi i32 [ %.1237407, %71 ], [ %.2238, %82 ]
%83 = freeze i32 %.1237.lcssa
br label %.critedge4

.critedge4:; preds = %.critedge4.loopexit, %.preheader400
%.1237.lcssa = phi i32 [ %.0236413, %.preheader400 ], [ %83, %.critedge4.loopexit ]
%84 = getelementptr inbounds nuw i8, ptr %61, i64 36
%85 = load i32, ptr %84, align 4, !tbaa !73
%86 = sext i32 %85 to i64
%87 = getelementptr inbounds i32, ptr %calloc, i64 %86
%88 = load i32, ptr %87, align 4, !tbaa !68
%89 = and i32 %88, 1431655765
%90 = lshr i32 %88, 1
%91 = and i32 %90, 1431655765
%92 = add nuw i32 %91, %89
%93 = and i32 %92, 858993459
%94 = lshr i32 %92, 2
%95 = and i32 %94, 858993459
%96 = add nuw nsw i32 %95, %93
%97 = and i32 %96, 117901063
%98 = lshr i32 %96, 4
%99 = and i32 %98, 117901063
%100 = add nuw nsw i32 %99, %97
%101 = and i32 %100, 983055
%102 = lshr i32 %100, 8
%103 = and i32 %102, 983055
%104 = add nuw nsw i32 %103, %101
%105 = and i32 %104, 31
%106 = lshr i32 %104, 16
%107 = add i32 %106, %.0234414
%108 = add i32 %107, %105
br label %109

109: ; preds = %.critedge4, %63, %59
%.3239 = phi i32 [ %.0236413, %59 ], [ %108, %.critedge4 ], [ %.0236413, %63 ]
%.1235 = phi i32 [ %.0234414, %59 ], [ %107, %.critedge4 ], [ %.0234414, %63 ]
%.3239 = phi i32 [ %.0236413, %59 ], [ %.1237.lcssa, %.critedge4 ], [ %.0236413, %63 ]
%.1235 = phi i32 [ %.0234414, %59 ], [ %108, %.critedge4 ], [ %.0234414, %63 ]
%indvars.iv.next455 = add nuw nsw i64 %indvars.iv454, 1
%exitcond458.not = icmp eq i64 %indvars.iv.next455, %wide.trip.count457
br i1 %exitcond458.not, label %.critedge2, label %59, !llvm.loop !76
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5 changes: 2 additions & 3 deletions bench/abseil-cpp/optimized/int128_test.ll
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Expand Up @@ -71751,8 +71751,7 @@ _ZNKSt14default_deleteINSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEE
store i64 %.sroa.2.0.extract.trunc.i1134, ptr %1047, align 8
call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %92) #27
%.sroa.01.0.insert.insert.i1132.frozen = freeze i128 %.sroa.01.0.insert.insert.i1132
%.frozen = freeze i128 %1104
%1106 = sdiv i128 %.sroa.01.0.insert.insert.i1132.frozen, %.frozen
%1106 = sdiv i128 %.sroa.01.0.insert.insert.i1132.frozen, %1104
%.sroa.2.0.extract.shift.i1146 = lshr i128 %1106, 64
%.sroa.2.0.extract.trunc.i1147 = trunc nuw i128 %.sroa.2.0.extract.shift.i1146 to i64
%.sroa.012.0.extract.trunc.i1148 = trunc i128 %1106 to i64
Expand Down Expand Up @@ -72264,7 +72263,7 @@ _ZNKSt14default_deleteINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEEclEP
store i64 %.sroa.0.0.insert.ext.i16.i, ptr %101, align 16
store i64 %.sroa.2.0.extract.shift.i1246, ptr %1060, align 8
call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %102) #27
%1256 = mul i128 %1106, %.frozen
%1256 = mul i128 %1106, %1104
%.decomposed1644 = sub i128 %.sroa.01.0.insert.insert.i1132.frozen, %1256
%.sroa.2.0.extract.shift.i1257 = lshr i128 %.decomposed1644, 64
%.sroa.2.0.extract.trunc.i1258 = trunc nuw i128 %.sroa.2.0.extract.shift.i1257 to i64
Expand Down
2 changes: 1 addition & 1 deletion bench/actix-rs/optimized/3k33h0ss7dy62evb.ll
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Expand Up @@ -1321,7 +1321,7 @@ define hidden { ptr, i64 } @"_ZN4core3str21_$LT$impl$u20$str$GT$12trim_matches17
%.not35 = phi i1 [ true, %2 ], [ true, %32 ], [ false, %"_ZN53_$LT$F$u20$as$u20$core..str..pattern..MultiCharEq$GT$7matches17h0eeeb9eb726f10eeE.llvm.906605461179275197.exit.i.i" ], [ false, %49 ], [ false, %47 ]
%.sroa.4.033 = phi ptr [ %0, %2 ], [ %34, %32 ], [ %.sink18.i.i, %"_ZN53_$LT$F$u20$as$u20$core..str..pattern..MultiCharEq$GT$7matches17h0eeeb9eb726f10eeE.llvm.906605461179275197.exit.i.i" ], [ %.sink18.i.i, %49 ], [ %.sink18.i.i, %47 ]
%.sroa.16.131 = phi i64 [ 0, %2 ], [ %.sroa.16.0, %32 ], [ %46, %"_ZN53_$LT$F$u20$as$u20$core..str..pattern..MultiCharEq$GT$7matches17h0eeeb9eb726f10eeE.llvm.906605461179275197.exit.i.i" ], [ %46, %49 ], [ %46, %47 ]
%.sroa.415.029 = phi i64 [ undef, %2 ], [ undef, %32 ], [ %.sroa.16.0, %"_ZN53_$LT$F$u20$as$u20$core..str..pattern..MultiCharEq$GT$7matches17h0eeeb9eb726f10eeE.llvm.906605461179275197.exit.i.i" ], [ %.sroa.16.0, %49 ], [ %.sroa.16.0, %47 ]
%.sroa.415.029 = phi i64 [ undef, %2 ], [ %.sroa.16.0, %47 ], [ %.sroa.16.0, %49 ], [ %.sroa.16.0, %"_ZN53_$LT$F$u20$as$u20$core..str..pattern..MultiCharEq$GT$7matches17h0eeeb9eb726f10eeE.llvm.906605461179275197.exit.i.i" ], [ %.sroa.16.0, %32 ]
%70 = phi i64 [ 0, %2 ], [ 0, %32 ], [ %46, %"_ZN53_$LT$F$u20$as$u20$core..str..pattern..MultiCharEq$GT$7matches17h0eeeb9eb726f10eeE.llvm.906605461179275197.exit.i.i" ], [ %46, %49 ], [ %46, %47 ]
%71 = icmp eq ptr %.sroa.4.033, %3
br i1 %71, label %.loopexit, label %.lr.ph.i9
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7 changes: 3 additions & 4 deletions bench/assimp/optimized/3DSConverter.ll
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Expand Up @@ -163,9 +163,9 @@ define hidden void @_ZN6Assimp19Discreet3DSImporter22ReplaceDefaultMaterialEv(pt
br label %21

._crit_edge77: ; preds = %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
%13 = icmp eq i32 %.127.fr, -842150451
%13 = icmp eq i32 %.127, -842150451
%14 = trunc nuw i64 %99 to i32
%spec.select = select i1 %13, i32 %14, i32 %.127.fr
%spec.select = select i1 %13, i32 %14, i32 %.127
br label %._crit_edge77.thread

._crit_edge77.thread: ; preds = %._crit_edge77, %1
Expand All @@ -181,7 +181,7 @@ define hidden void @_ZN6Assimp19Discreet3DSImporter22ReplaceDefaultMaterialEv(pt
21: ; preds = %.lr.ph76, %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
%22 = phi ptr [ %10, %.lr.ph76 ], [ %95, %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit ]
%23 = phi i64 [ 0, %.lr.ph76 ], [ %91, %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit ]
%.02674 = phi i32 [ -842150451, %.lr.ph76 ], [ %.127.fr, %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit ]
%.02674 = phi i32 [ -842150451, %.lr.ph76 ], [ %.127, %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit ]
%.02972 = phi i32 [ 0, %.lr.ph76 ], [ %90, %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit ]
call void @llvm.lifetime.start.p0(i64 32, ptr nonnull %3) #26
%24 = getelementptr inbounds nuw %"struct.Assimp::D3DS::Material", ptr %22, i64 %23, i32 1
Expand Down Expand Up @@ -305,7 +305,6 @@ _ZNK6Assimp19Discreet3DSImporter16ContainsTexturesEj.exit.thread: ; preds = %61,

83: ; preds = %_ZNK6Assimp19Discreet3DSImporter16ContainsTexturesEj.exit.thread, %_ZNK6Assimp19Discreet3DSImporter16ContainsTexturesEj.exit, %48, %57, %._crit_edge
%.127 = phi i32 [ %.02674, %._crit_edge ], [ %.02674, %57 ], [ %.02674, %48 ], [ %.02674, %_ZNK6Assimp19Discreet3DSImporter16ContainsTexturesEj.exit.thread ], [ %.02972, %_ZNK6Assimp19Discreet3DSImporter16ContainsTexturesEj.exit ]
%.127.fr = freeze i32 %.127
%84 = load ptr, ptr %3, align 8
%85 = icmp eq ptr %84, %11
br i1 %85, label %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.thread.i.i, label %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i
Expand Down
88 changes: 39 additions & 49 deletions bench/assimp/optimized/ComputeUVMappingProcess.ll
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Expand Up @@ -117,63 +117,52 @@ define hidden void @_Z13RemoveUVSeamsP6aiMeshP10aiVector3tIfE(ptr noundef readon
%wide.trip.count = zext i32 %9 to i64
br label %31

13: ; preds = %46
13: ; preds = %42
%.not = icmp eq i32 %.175, %9
%.not81 = icmp eq i32 %.173, %9
%or.cond82 = select i1 %.not, i1 true, i1 %.not81
br i1 %or.cond82, label %.loopexit, label %.lr.ph

.lr.ph: ; preds = %13
%or.cond5 = select i1 %.169, i1 %.171, i1 false
%or.cond5.fr = freeze i1 %or.cond5
br i1 %or.cond5.fr, label %.lr.ph.split.us, label %.lr.ph.split
br i1 %or.cond5, label %.lr.ph.split.us, label %.lr.ph.split

.lr.ph.split.us: ; preds = %.lr.ph, %27
%indvars.iv103 = phi i64 [ %indvars.iv.next104, %27 ], [ 0, %.lr.ph ]
%indvars.iv103 = phi i64 [ %indvars.iv.next104, %23 ], [ 0, %.lr.ph ]
%14 = load ptr, ptr %11, align 8
%15 = getelementptr inbounds nuw i32, ptr %14, i64 %indvars.iv103
%16 = load i32, ptr %15, align 4
%17 = zext i32 %16 to i64
%18 = getelementptr inbounds nuw %class.aiVector3t, ptr %1, i64 %17
%19 = load float, ptr %18, align 4
%20 = fcmp ule float %19, 0x3FECCCCCC0000000
%or.cond.us = select i1 %20, i1 true, i1 %.171
br i1 %or.cond.us, label %21, label %.sink.split
%20 = fcmp oge float %19, 0x3FEFAE1480000000
%or.cond84.not.us = and i1 %.1, %20
br i1 %or.cond84.not.us, label %23, label %21

21: ; preds = %.lr.ph.split.us
%22 = fcmp uge float %19, 0x3FB99999A0000000
%or.cond3.us = select i1 %22, i1 true, i1 %.169
br i1 %or.cond3.us, label %23, label %.sink.split

23: ; preds = %21
%24 = fcmp oge float %19, 0x3FEFAE1480000000
%or.cond84.not.us = and i1 %.1, %24
br i1 %or.cond84.not.us, label %.sink.split, label %25

25: ; preds = %23
%26 = fcmp ugt float %19, 0x3F847AE140000000
%or.cond85.us = or i1 %.1, %26
br i1 %or.cond85.us, label %27, label %.sink.split

.sink.split: ; preds = %23, %25, %21, %.lr.ph.split.us
%.sink = phi float [ 0.000000e+00, %.lr.ph.split.us ], [ 1.000000e+00, %21 ], [ 1.000000e+00, %25 ], [ 0.000000e+00, %23 ]
%22 = fcmp ugt float %19, 0x3F847AE140000000
%or.cond85.us = or i1 %.1, %22
br i1 %or.cond85.us, label %23, label %.sink.split

23: ; preds = %.lr.ph.split.us, %21
%.sink = phi float [ 1.000000e+00, %21 ], [ 0.000000e+00, %.lr.ph.split.us.preheader ]
store float %.sink, ptr %18, align 4
br label %27

27: ; preds = %.sink.split, %25
27: ; preds = %.sink.split, %21
%indvars.iv.next104 = add nuw nsw i64 %indvars.iv103, 1
%28 = load i32, ptr %8, align 8
%29 = zext i32 %28 to i64
%30 = icmp samesign ult i64 %indvars.iv.next104, %29
br i1 %30, label %.lr.ph.split.us, label %.loopexit, !llvm.loop !3

31: ; preds = %.preheader87, %46
%indvars.iv = phi i64 [ 0, %.preheader87 ], [ %indvars.iv.next, %46 ]
%.06792 = phi i1 [ false, %.preheader87 ], [ %.1, %46 ]
%.06891 = phi i1 [ false, %.preheader87 ], [ %.169, %46 ]
%.07090 = phi i1 [ false, %.preheader87 ], [ %.171, %46 ]
%.07289 = phi i32 [ %9, %.preheader87 ], [ %.173, %46 ]
%.07488 = phi i32 [ %9, %.preheader87 ], [ %.175, %46 ]
31: ; preds = %.preheader87, %42
%indvars.iv = phi i64 [ 0, %.preheader87 ], [ %indvars.iv.next, %42 ]
%.06792 = phi i1 [ false, %.preheader87 ], [ %.1, %42 ]
%.06891 = phi i1 [ false, %.preheader87 ], [ %.169, %42 ]
%.07090 = phi i1 [ false, %.preheader87 ], [ %.171, %42 ]
%.07289 = phi i32 [ %9, %.preheader87 ], [ %.173, %42 ]
%.07488 = phi i32 [ %9, %.preheader87 ], [ %.175, %42 ]
%32 = getelementptr inbounds nuw i32, ptr %12, i64 %indvars.iv
%33 = load i32, ptr %32, align 4
%34 = zext i32 %33 to i64
Expand All @@ -185,28 +174,29 @@ define hidden void @_Z13RemoveUVSeamsP6aiMeshP10aiVector3tIfE(ptr noundef readon
%39 = trunc nuw i64 %indvars.iv to i32
%.175 = select i1 %37, i32 %39, i32 %.07488
%40 = and i1 %37, %not.
%.171 = select i1 %40, i1 true, i1 %.07090
%41 = and i1 %37, %38
%.1 = select i1 %41, i1 true, i1 %.06792
%42 = fcmp ogt float %36, 0x3FECCCCCC0000000
br i1 %42, label %43, label %46

43: ; preds = %31
%44 = fcmp ult float %36, 0x3FEFAE1480000000
br i1 %44, label %46, label %45

45: ; preds = %43
br label %46

46: ; preds = %31, %45, %43
%.173 = phi i32 [ %39, %45 ], [ %39, %43 ], [ %.07289, %31 ]
%.169 = phi i1 [ true, %45 ], [ %.06891, %43 ], [ %.06891, %31 ]
%.fr = freeze i1 %40
%.171 = select i1 %.fr, i1 true, i1 %.07090
%37 = and i1 %33, %34
%.1 = select i1 %37, i1 true, i1 %.06792
%38 = fcmp ogt float %36, 0x3FECCCCCC0000000
br i1 %38, label %39, label %42

39:; preds = %31
%40 = fcmp ult float %36, 0x3FEFAE1480000000
br i1 %40, label %42, label %41

41:; preds = %39
br label %42

42:; preds = %27, %41, %39
%.169 = phi i32 [ %35, %41 ], [ %35, %39 ], [ %.07289, %27 ]
%.169 = phi i1 [ true, %41 ], [ %.06891, %39 ], [ %.06891, %27 ]
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
br i1 %exitcond.not, label %13, label %31, !llvm.loop !6

.lr.ph.split: ; preds = %.lr.ph, %56
%indvars.iv100 = phi i64 [ %indvars.iv.next101, %56 ], [ 0, %.lr.ph ]
%indvars.iv100 = phi i64 [ %indvars.iv.next101, %52 ], [ 0, %.lr.ph ]
%47 = load ptr, ptr %11, align 8
%48 = getelementptr inbounds nuw i32, ptr %47, i64 %indvars.iv100
%49 = load i32, ptr %48, align 4
Expand All @@ -223,7 +213,7 @@ define hidden void @_Z13RemoveUVSeamsP6aiMeshP10aiVector3tIfE(ptr noundef readon
br i1 %or.cond3, label %56, label %.sink.split110

.sink.split110: ; preds = %54, %.lr.ph.split
%.sink111 = phi float [ 0.000000e+00, %.lr.ph.split ], [ 1.000000e+00, %54 ]
%.sink111 = phi float [ 0.000000e+00, %.lr.ph.split ], [ 1.000000e+00, %50 ]
store float %.sink111, ptr %51, align 4
br label %56

Expand Down
18 changes: 7 additions & 11 deletions bench/boost/optimized/ipv6_address_rule.ll
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Expand Up @@ -90,7 +90,7 @@ define void @_ZNK5boost4urls22implementation_defined19ipv6_address_rule_t5parseE
%.promoted = phi ptr [ %11, %4 ], [ %.promoted.pre, %.outer.backedge ]
%.076.ph = phi ptr [ %11, %4 ], [ %.076.ph.be, %.outer.backedge ]
%.074.ph = phi i1 [ false, %4 ], [ true, %.outer.backedge ]
%.072.ph = phi i32 [ -1, %4 ], [ %.072345, %.outer.backedge ]
%.072.ph = phi i32 [ -1, %4 ], [ %.072, %.outer.backedge ]
%.0.ph = phi i32 [ 8, %4 ], [ %.0.ph.be, %.outer.backedge ]
br label %12

Expand Down Expand Up @@ -295,7 +295,6 @@ _ZNKR5boost6system6resultINS_4urls6detail10h16_rule_t10value_typeENS0_10error_co
br i1 %76, label %.thread245, label %.outer.backedge

.outer.backedge: ; preds = %.cont195, %.cont
%.072345 = phi i32 [ %.072344, %.cont ], [ %.072, %.cont195 ]
%.076.ph.be = phi ptr [ %13, %.cont ], [ %29, %.cont195 ]
%.0.ph.be = phi i32 [ %159, %.cont ], [ %75, %.cont195 ]
%.promoted.pre = load ptr, ptr %2, align 8, !tbaa !3
Expand Down Expand Up @@ -476,7 +475,6 @@ _ZN5boost4urls7grammar12hexdig_valueEc.exit: ; preds = %26
br i1 %.not273, label %_ZN5boost4urls7grammar12hexdig_valueEc.exit.thread, label %.thread258

_ZN5boost4urls7grammar12hexdig_valueEc.exit.thread: ; preds = %26, %26, %26, %26, %26, %26, %26, %26, %26, %26, %26, %26, %26, %26, %26, %26, %26, %26, %26, %26, %26, %26, %_ZN5boost4urls7grammar12hexdig_valueEc.exit
%.072344 = phi i32 [ -1, %_ZN5boost4urls7grammar12hexdig_valueEc.exit ], [ %.072, %26 ], [ %.072, %26 ], [ %.072, %26 ], [ %.072, %26 ], [ %.072, %26 ], [ %.072, %26 ], [ %.072, %26 ], [ %.072, %26 ], [ %.072, %26 ], [ %.072, %26 ], [ %.072, %26 ], [ %.072, %26 ], [ %.072, %26 ], [ %.072, %26 ], [ %.072, %26 ], [ %.072, %26 ], [ %.072, %26 ], [ %.072, %26 ], [ %.072, %26 ], [ %.072, %26 ], [ %.072, %26 ], [ %.072, %26 ]
br i1 %.074, label %161, label %145

145: ; preds = %_ZN5boost4urls7grammar12hexdig_valueEc.exit.thread
Expand Down Expand Up @@ -558,9 +556,8 @@ _ZN5boost6system10error_codeC2ERKS1_PKNS_15source_locationE.exit132: ; preds = %
br label %.thread232

.thread245: ; preds = %.cont, %.cont195, %.thread
%.072342 = phi i32 [ %.072, %.thread ], [ %.072344, %.cont ], [ %.072, %.cont195 ]
%.1 = phi i32 [ %142, %.thread ], [ 0, %.cont195 ], [ 0, %.cont ]
%171 = icmp eq i32 %.072342, -1
%171 = icmp eq i32 %.072, -1
br i1 %171, label %172, label %.thread258

172: ; preds = %.thread245
Expand All @@ -570,13 +567,12 @@ _ZN5boost6system10error_codeC2ERKS1_PKNS_15source_locationE.exit132: ; preds = %
br label %.thread232

.thread258: ; preds = %_ZN5boost4urls7grammar12hexdig_valueEc.exit, %15, %.thread245
%.072341 = phi i32 [ %.072342, %.thread245 ], [ %.072, %15 ], [ %.072, %_ZN5boost4urls7grammar12hexdig_valueEc.exit ]
%.1262 = phi i32 [ %.1, %.thread245 ], [ %.0, %15 ], [ %.0, %_ZN5boost4urls7grammar12hexdig_valueEc.exit ]
%174 = icmp eq i32 %.072341, %.1262
%174 = icmp eq i32 %.072, %.1262
br i1 %174, label %.thread258.thread, label %181

.thread258.thread: ; preds = %46, %.thread258
%.1262267 = phi i32 [ %.072341, %.thread258 ], [ 0, %46 ]
%.1262267 = phi i32 [ %.072, %.thread258 ], [ 0, %46 ]
%175 = shl i32 %.1262267, 1
%176 = sub i32 14, %175
%177 = sext i32 %176 to i64
Expand All @@ -587,7 +583,7 @@ _ZN5boost6system10error_codeC2ERKS1_PKNS_15source_locationE.exit132: ; preds = %
br label %207

181: ; preds = %.thread258
%182 = icmp eq i32 %.072341, 7
%182 = icmp eq i32 %.072, 7
br i1 %182, label %183, label %191

183: ; preds = %181
Expand All @@ -603,9 +599,9 @@ _ZN5boost6system10error_codeC2ERKS1_PKNS_15source_locationE.exit132: ; preds = %
br label %207

191: ; preds = %181
%192 = shl i32 %.072341, 1
%192 = shl i32 %.072, 1
%193 = sub i32 14, %192
%194 = sub nsw i32 %.072341, %.1262
%194 = sub nsw i32 %.072, %.1262
%195 = shl nsw i32 %194, 1
%196 = sub nsw i32 16, %195
%197 = sext i32 %196 to i64
Expand Down
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