pre-commit: PR155176

[zyw-bot]

Link: llvm/llvm-project#155176
Requested by: @dtcxzyw

[zyw-bot]

Diff mode

runner: ariselab-64c-docker
baseline: llvm/llvm-project@a7a1781
patch: llvm/llvm-project#155176
sha256: 3336b46b7407e2c70c36abef80a80ef769d254fdce0cb80aef3e32b967a9efc1
commit: 09568a2

185 files changed, 302778 insertions(+), 304768 deletions(-)

Improvements:
  bdce.NumRemoved 386558 -> 386802 +0.06%
  bdce.NumSimplified 6004 -> 6007 +0.05%
  gvn.NumGVNLoad 1379500 -> 1380088 +0.04%
  memdep.NumCacheCompleteNonLocalPtr 5512166 -> 5513722 +0.03%
  instcombine.NumFactor 45368 -> 45379 +0.02%
  memdep.NumCacheNonLocal 21054 -> 21059 +0.02%
  dse.NumRedundantStores 36391 -> 36395 +0.01%
  local.NumPHICSEs 198991 -> 199006 +0.01%
  instcombine.NumSunkInst 3487296 -> 3487511 +0.01%
  instcombine.NegatorMaxDepthVisited 20318 -> 20319 +0.00%
Regressions:
  simple-loop-unswitch.NumSwitches 1966 -> 1965 -0.05%
  simple-loop-unswitch.NumCostMultiplierSkipped 17715 -> 17709 -0.03%
  reassociate.NumChanged 5100535 -> 5099796 -0.01%
  correlated-value-propagation.NumSMinMax 9207 -> 9206 -0.01%
  gvn.NumGVNInstr 155772 -> 155757 -0.01%
  gvn.NumGVNPRE 155772 -> 155757 -0.01%
  gvn.NumGVNEqProp 441408 -> 441366 -0.01%
  sccp.NumDeadBlocks 707380 -> 707318 -0.01%
  correlated-value-propagation.NumMinMax 12250 -> 12249 -0.01%
  licm.NumHoisted 5463796 -> 5463449 -0.01%

38 63 bench/actix-rs/optimized/5dylu5g0crehei80.ll
93 112 bench/boost/optimized/get_turns_areal_areal.ll
30 35 bench/cmake/optimized/archive_read_support_format_zip.ll
58 79 bench/cpython/optimized/Hacl_Hash_Blake2b.ll
33 55 bench/cpython/optimized/Hacl_Hash_Blake2b_Simd256.ll
33 37 bench/cpython/optimized/Hacl_Hash_Blake2s_Simd128.ll
16 19 bench/duckdb/optimized/regexp.ll
46 49 bench/ffmpeg/optimized/avformat.ll
5 10 bench/ffmpeg/optimized/mpeg.ll
20 23 bench/ffmpeg/optimized/vf_detelecine.ll
23 24 bench/hdf5/optimized/H5HFcache.ll
81 84 bench/imgui/optimized/imgui_widgets.ll
17 29 bench/just-rs/optimized/1uppz7l1e89fp8n7.ll
9 15 bench/just-rs/optimized/uwydcyn8qeoqoev.ll
34 36 bench/linux/optimized/addrconf.ll
21 23 bench/linux/optimized/generic.ll
29 32 bench/linux/optimized/x86_pkg_temp_thermal.ll
37 39 bench/llvm/optimized/AArch64PBQPRegAlloc.ll
3 13 bench/llvm/optimized/SemaDecl.ll
6 26 bench/llvm/optimized/SemaDeclCXX.ll
19 28 bench/meshlab/optimized/filter_icp.ll
28 31 bench/meshlab/optimized/load_save.ll
10 11 bench/minetest/optimized/client.ll
16 19 bench/minetest/optimized/guiChatConsole.ll
18 20 bench/minetest/optimized/pathfinder.ll
4 11 bench/minetest/optimized/test_sao.ll
12 18 bench/msdfgen/optimized/msdf-error-correction.ll
28 31 bench/opencv/optimized/grabcut.ll
27 31 bench/opencv/optimized/perf_reduce.ll
56 60 bench/opencv/optimized/perf_threshold.ll
16 14 bench/opencv/optimized/sparse_match_interpolators.ll
62 66 bench/openssl/optimized/ofb64ede.ll
62 66 bench/openssl/optimized/ofb64enc.ll
62 66 bench/openssl/optimized/rc2ofb64.ll
8 16 bench/openusd/optimized/avif.ll
10 12 bench/openusd/optimized/prim.ll
58 75 bench/pola-rs/optimized/14pqkeep8nux61uultru6rglq.ll
36 68 bench/pola-rs/optimized/3j6s1s8bkufqpw2g2hh1cvgea.ll
102 94 bench/rayon-rs/optimized/1j5m2t9gtbur4l2z.ll
11 14 bench/re2/optimized/regexp.ll
82 119 bench/regex-rs/optimized/1x04d8372kemp7hd.ll
16 19 bench/rust-analyzer-rs/optimized/1g0h5ha3lba2bol5.ll
24 45 bench/rust-analyzer-rs/optimized/357j944nkpwuonjr.ll
89 92 bench/rust-analyzer-rs/optimized/3eest3j1daftelre.ll
37 36 bench/rust-analyzer-rs/optimized/46lti8aa4smufhcb.ll
31 49 bench/rust-analyzer-rs/optimized/ax17c37uj31hhic.ll
54 68 bench/typst-rs/optimized/m09o5qr68f5khss.ll
20 23 bench/wasmtime-rs/optimized/24tijvi11z3k9odl.ll
36 40 bench/wasmtime-rs/optimized/4v5zacq1pia1727a.ll
32 50 bench/yara-x-rs/optimized/0n2x7v66evj4ga77peh4kez74.ll
24 30 bench/yara-x-rs/optimized/7kdrv2ks7wriy60c55s9rwzp3.ll
11 14 bench/yara-x-rs/optimized/cco05ky1qb53ayhfyotquzvcb.ll
24 27 bench/zed-rs/optimized/3hzvg0vxovkxolvfr6bwvtv1m.ll
13 15 bench/zed-rs/optimized/9k41n0dnz3hh6kxq426e2leu5.ll
13 15 bench/zed-rs/optimized/b1zstcip87cpnqp265tsc7n2q.ll
6 19 bench/zed-rs/optimized/dw4qzuo904yf8wu71sutofhxl.ll
15 17 bench/zed-rs/optimized/eio6txv0nku2we5mnjcgiiw85.ll
2 2 bench/zed-rs/optimized/f14rkn3hjaifgtm5q8vihlx5s.ll
16 18 bench/zed-rs/optimized/f3wmqxw6x607w7cbx1edvfc95.ll

[github-actions]

The provided diff shows several optimizations across multiple LLVM IR files. Here are the major changes summarized:

1. Load and Store Optimization: In multiple files, sequences of 8-bit and 56-bit loads and stores are replaced with single 64-bit operations. This reduces the number of memory operations and improves performance by leveraging wider data paths.

2. Alignment Adjustments: Several alloca instructions have their alignment increased from 4 to 8 bytes, which can improve memory access efficiency on architectures that benefit from higher alignment.

3. Reduction of Bit Manipulation: Complex sequences involving zext, shl, and or operations to combine smaller integers into larger ones are simplified. For example, operations that construct a 64-bit value from two 32-bit values are streamlined.

4. Phi Node Simplification: Phi nodes in control flow are simplified, reducing the number of incoming values and making the control flow more straightforward.

5. Function Call Simplification: Some function calls are optimized by reducing the number of parameters or simplifying the parameter passing mechanism, which can reduce call overhead.

These changes collectively aim to improve performance by reducing the number of instructions, improving memory access patterns, and simplifying control flow.

model: qwen-plus-latest
CompletionUsage(completion_tokens=254, prompt_tokens=113024, total_tokens=113278, completion_tokens_details=None, prompt_tokens_details=None)