pre-commit: PR156477

[zyw-bot]

Link: llvm/llvm-project#156477
Requested by: @OutOfCache

[zyw-bot]

Diff mode

runner: ariselab-64c-docker
baseline: llvm/llvm-project@a0b8d54
patch: llvm/llvm-project#156477
sha256: 058e917b21301c1725d7cf41f38274c8f9d008896014deffe1c69a59192e5547
commit: aaa1e3d

46 files changed, 12314 insertions(+), 13002 deletions(-)

Improvements:
  simplifycfg.NumBitMaps 2229 -> 2282 +2.38%
  simplifycfg.NumLookupTablesHoles 2611 -> 2625 +0.54%
  simplifycfg.NumLinearMaps 3969 -> 3986 +0.43%
  instcombine.NegatorMaxDepthVisited 20188 -> 20189 +0.00%
  simplifycfg.NumFoldBranchToCommonDest 772634 -> 772647 +0.00%
  instcombine.NegatorMaxTotalValuesVisited 62520 -> 62521 +0.00%
  instcombine.NumReassoc 285779 -> 285782 +0.00%
  instcombine.NumSunkInst 3485171 -> 3485199 +0.00%
  simplifycfg.NumSpeculations 408033 -> 408034 +0.00%
  instcombine.NumCombined 125674505 -> 125674807 +0.00%
Regressions:
  simplifycfg.NumLookupTables 22509 -> 19557 -13.11%
  last-run-tracking.NumSkippedPasses 50281363 -> 50281330 -0.00%

8 13 bench/linux/optimized/8250_pci.ll
169 184 bench/linux/optimized/acpi_video.ll
242 254 bench/linux/optimized/auditfilter.ll
11 14 bench/linux/optimized/bugs.ll
23 56 bench/linux/optimized/drm_dp_helper.ll
56 118 bench/linux/optimized/drm_mipi_dsi.ll
6 15 bench/linux/optimized/exthdrs_core.ll
34 47 bench/linux/optimized/fcntl.ll
42 59 bench/linux/optimized/g4x_dp.ll
125 128 bench/linux/optimized/hda_controller.ll
177 176 bench/linux/optimized/intel_ddi.ll
7 9 bench/linux/optimized/intel_dp.ll
47 67 bench/linux/optimized/intel_dp_link_training.ll
93 100 bench/linux/optimized/intel_hdmi.ll
175 199 bench/linux/optimized/intel_overlay.ll
77 90 bench/linux/optimized/intel_rps.ll
47 41 bench/linux/optimized/intel_sseu.ll
137 135 bench/linux/optimized/ip_tunnel_core.ll
42 41 bench/linux/optimized/keyctl.ll
47 39 bench/linux/optimized/kstrtox.ll
91 90 bench/linux/optimized/libata-pmp.ll
13 13 bench/linux/optimized/md.ll
87 99 bench/linux/optimized/nfs4proc.ll
12 17 bench/linux/optimized/open.ll
8 8 bench/linux/optimized/pcm_native.ll
29 61 bench/linux/optimized/policy.ll
166 174 bench/linux/optimized/psargs.ll
108 119 bench/linux/optimized/rx.ll
256 285 bench/linux/optimized/scsi_lib.ll
18 23 bench/linux/optimized/services.ll
57 75 bench/linux/optimized/skl_universal_plane.ll
28 39 bench/linux/optimized/skl_watermark.ll
89 106 bench/linux/optimized/sky2.ll
54 67 bench/linux/optimized/string_helpers.ll
24 60 bench/linux/optimized/tty_ioctl.ll
156 162 bench/linux/optimized/tx.ll
14 31 bench/linux/optimized/vht.ll
68 113 bench/linux/optimized/virtio_blk.ll
275 296 bench/linux/optimized/vlv_dsi.ll

[github-actions]

The provided diff shows a transformation of LLVM IR from using switch instructions to more optimized patterns involving bit manipulation and conditional selects. Here are the major changes:

1. Switch-to-Bitmask Optimization: Multiple switch statements across various functions (e.g., pci_moxa_init, acpi_video_bus_get_one_device, audit_del_rule) are replaced with sequences using icmp ult, shift, and bit masking operations. This avoids jump tables and enables constant-time dispatch via bit extraction.

2. Elimination of Redundant Blocks: Basic blocks associated with switch fallthrough cases (e.g., 11, 53, 54, 55, 56) are removed. Their logic is folded into direct computations using select and bit shifts, reducing control flow complexity.

3. Use of Large Integer Types for Bit Encoding: Values from switch cases are encoded into wide integers (e.g., i56, i40, i63), right-shifted by computed amounts, and truncated to extract the correct result. This allows compact encoding of sparse case values.

4. Improved Phi Node Usage: Phi nodes are simplified by removing entries for eliminated blocks. For example, in acpi_video_bus_get_one_device, phi nodes now have fewer incoming values due to collapsed control flow paths.

5. Code Size and Performance Optimization: The new pattern reduces the number of basic blocks and branches, favoring arithmetic and bitwise operations. This likely improves instruction cache usage and enables better downstream optimization, especially for small, dense switch cases.

These changes reflect a peephole optimization pass that transforms small-range switches into branchless, arithmetic-based dispatch, improving performance on architectures where branching is expensive.

model: qwen-plus-latest
CompletionUsage(completion_tokens=362, prompt_tokens=109184, total_tokens=109546, completion_tokens_details=None, prompt_tokens_details=None)

[nikic]

The new transforms are all in linux/ which uses no-jump-tables, so this is expected.

/close