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[RISCV] Verify vfwmaccbf16 and vfncvtbf16 FRM argument in SemaRISCV::CheckBuiltinFunctionCall. (llvm#155710)
We need to check that the FRM value is an integer constant expression with value 0-4.
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‎clang/lib/Sema/SemaRISCV.cpp‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1000,6 +1000,7 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI,
10001000
case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm:
10011001
case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm:
10021002
case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm:
1003+
case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm:
10031004
return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 4);
10041005
case RISCVVector::BI__builtin_rvv_vfadd_vv_rm:
10051006
case RISCVVector::BI__builtin_rvv_vfadd_vf_rm:
@@ -1038,6 +1039,7 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI,
10381039
case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_tu:
10391040
case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_tu:
10401041
case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_tu:
1042+
case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_tu:
10411043
case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_m:
10421044
case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_m:
10431045
case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_m:
@@ -1051,6 +1053,7 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI,
10511053
case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_m:
10521054
case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_m:
10531055
case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_m:
1056+
case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_m:
10541057
return SemaRef.BuiltinConstantArgRange(TheCall, 2, 0, 4);
10551058
case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tu:
10561059
case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tu:
@@ -1100,6 +1103,8 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI,
11001103
case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm:
11011104
case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm:
11021105
case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm:
1106+
case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm:
1107+
case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm:
11031108
case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_tu:
11041109
case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_tu:
11051110
case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_tu:
@@ -1124,6 +1129,8 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI,
11241129
case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_tu:
11251130
case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_tu:
11261131
case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_tu:
1132+
case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_tu:
1133+
case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_tu:
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case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_m:
11281135
case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_m:
11291136
case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_m:
@@ -1161,6 +1168,7 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI,
11611168
case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_tum:
11621169
case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_tum:
11631170
case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_tum:
1171+
case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_tum:
11641172
case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_tumu:
11651173
case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_tumu:
11661174
case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_tumu:
@@ -1174,6 +1182,7 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI,
11741182
case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_tumu:
11751183
case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_tumu:
11761184
case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_tumu:
1185+
case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_tumu:
11771186
case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_mu:
11781187
case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_mu:
11791188
case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_mu:
@@ -1187,6 +1196,7 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI,
11871196
case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_mu:
11881197
case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_mu:
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case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_mu:
1199+
case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_mu:
11901200
return SemaRef.BuiltinConstantArgRange(TheCall, 3, 0, 4);
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case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_m:
11921202
case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_m:
@@ -1212,6 +1222,8 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI,
12121222
case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_m:
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case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_m:
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case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_m:
1225+
case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_m:
1226+
case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_m:
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case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tum:
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case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tum:
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case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tum:
@@ -1256,6 +1268,8 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI,
12561268
case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_tum:
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case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_tum:
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case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_tum:
1271+
case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_tum:
1272+
case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_tum:
12591273
case RISCVVector::BI__builtin_rvv_vfredosum_vs_rm_tum:
12601274
case RISCVVector::BI__builtin_rvv_vfredusum_vs_rm_tum:
12611275
case RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm_tum:
@@ -1304,6 +1318,8 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI,
13041318
case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_tumu:
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case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_tumu:
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case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_tumu:
1321+
case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_tumu:
1322+
case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_tumu:
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case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_mu:
13081324
case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_mu:
13091325
case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_mu:
@@ -1348,6 +1364,8 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI,
13481364
case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_mu:
13491365
case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_mu:
13501366
case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_mu:
1367+
case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_mu:
1368+
case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_mu:
13511369
return SemaRef.BuiltinConstantArgRange(TheCall, 4, 0, 4);
13521370
case RISCV::BI__builtin_riscv_ntl_load:
13531371
case RISCV::BI__builtin_riscv_ntl_store:

‎clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfncvtbf16-out-of-range.c‎

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,31 @@
1+
// requires: riscv-registered-target
2+
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
3+
// RUN: -target-feature +v -target-feature +zvfbfmin \
4+
// RUN: -fsyntax-only -verify %s
5+
6+
#include <riscv_vector.h>
7+
8+
vbfloat16m1_t test_vfncvtbf16_f_f_w_bf16m1_rm_m(vbool16_t mask, vfloat32m2_t src, size_t vl) {
9+
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
10+
return __riscv_vfncvtbf16_f_f_w_bf16m1_rm_m(mask, src, 5, vl);
11+
}
12+
13+
vbfloat16m1_t test_vfncvtbf16_f_f_w_bf16m1_rm_tu(vbfloat16m1_t maskedoff, vfloat32m2_t src, size_t vl) {
14+
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
15+
return __riscv_vfncvtbf16_f_f_w_bf16m1_rm_tu(maskedoff, src, 5, vl);
16+
}
17+
18+
vbfloat16m1_t test_vfncvtbf16_f_f_w_bf16m1_rm_tum(vbool16_t mask, vbfloat16m1_t maskedoff, vfloat32m2_t src, size_t vl) {
19+
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
20+
return __riscv_vfncvtbf16_f_f_w_bf16m1_rm_tum(mask, maskedoff, src, 5, vl);
21+
}
22+
23+
vbfloat16m1_t test_vfncvtbf16_f_f_w_bf16m1_rm_tumu(vbool16_t mask, vbfloat16m1_t maskedoff, vfloat32m2_t src, size_t vl) {
24+
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
25+
return __riscv_vfncvtbf16_f_f_w_bf16m1_rm_tumu(mask, maskedoff, src, 5, vl);
26+
}
27+
28+
vbfloat16m1_t test_vfncvtbf16_f_f_w_bf16m1_rm_mu(vbool16_t mask, vbfloat16m1_t maskedoff, vfloat32m2_t src, size_t vl) {
29+
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
30+
return __riscv_vfncvtbf16_f_f_w_bf16m1_rm_mu(mask, maskedoff, src, 5, vl);
31+
}

‎clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfwmaccbf16-out-of-range.c‎

Lines changed: 66 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,66 @@
1+
// REQUIRES: riscv-registered-target
2+
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
3+
// RUN: -target-feature +v -target-feature +zvfbfwma \
4+
// RUN: -fsyntax-only -verify %s
5+
6+
#include <riscv_vector.h>
7+
8+
vfloat32m1_t test_vfwmaccbf16_vv_f32m1_rm(vfloat32m1_t vd, vbfloat16mf2_t vs1, vbfloat16mf2_t vs2, size_t vl) {
9+
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
10+
return __riscv_vfwmaccbf16_vv_f32m1_rm(vd, vs1, vs2, 5, vl);
11+
}
12+
13+
vfloat32m1_t test_vfwmaccbf16_vf_f32m1_rm(vfloat32m1_t vd, __bf16 vs1, vbfloat16mf2_t vs2, size_t vl) {
14+
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
15+
return __riscv_vfwmaccbf16_vf_f32m1_rm(vd, vs1, vs2, 5, vl);
16+
}
17+
18+
vfloat32m1_t test_vfwmaccbf16_vv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, vbfloat16mf2_t vs1, vbfloat16mf2_t vs2, size_t vl) {
19+
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
20+
return __riscv_vfwmaccbf16_vv_f32m1_rm_m(mask, vd, vs1, vs2, 5, vl);
21+
}
22+
23+
vfloat32m1_t test_vfwmaccbf16_vf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, __bf16 vs1, vbfloat16mf2_t vs2, size_t vl) {
24+
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
25+
return __riscv_vfwmaccbf16_vf_f32m1_rm_m(mask, vd, vs1, vs2, 5, vl);
26+
}
27+
28+
vfloat32m1_t test_vfwmaccbf16_vv_f32m1_rm_tu(vfloat32m1_t vd, vbfloat16mf2_t vs1, vbfloat16mf2_t vs2, size_t vl) {
29+
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
30+
return __riscv_vfwmaccbf16_vv_f32m1_rm_tu(vd, vs1, vs2, 5, vl);
31+
}
32+
33+
vfloat32m1_t test_vfwmaccbf16_vf_f32m1_rm_tu(vfloat32m1_t vd, __bf16 vs1, vbfloat16mf2_t vs2, size_t vl) {
34+
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
35+
return __riscv_vfwmaccbf16_vf_f32m1_rm_tu(vd, vs1, vs2, 5, vl);
36+
}
37+
38+
vfloat32m1_t test_vfwmaccbf16_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, vbfloat16mf2_t vs1, vbfloat16mf2_t vs2, size_t vl) {
39+
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
40+
return __riscv_vfwmaccbf16_vv_f32m1_rm_tum(mask, vd, vs1, vs2, 5, vl);
41+
}
42+
43+
vfloat32m1_t test_vfwmaccbf16_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, __bf16 vs1, vbfloat16mf2_t vs2, size_t vl) {
44+
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
45+
return __riscv_vfwmaccbf16_vf_f32m1_rm_tum(mask, vd, vs1, vs2, 5, vl);
46+
}
47+
48+
vfloat32m1_t test_vfwmaccbf16_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, vbfloat16mf2_t vs1, vbfloat16mf2_t vs2, size_t vl) {
49+
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
50+
return __riscv_vfwmaccbf16_vv_f32m1_rm_tumu(mask, vd, vs1, vs2, 5, vl);
51+
}
52+
53+
vfloat32m1_t test_vfwmaccbf16_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, __bf16 vs1, vbfloat16mf2_t vs2, size_t vl) {
54+
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
55+
return __riscv_vfwmaccbf16_vf_f32m1_rm_tumu(mask, vd, vs1, vs2, 5, vl);
56+
}
57+
58+
vfloat32m1_t test_vfwmaccbf16_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, vbfloat16mf2_t vs1, vbfloat16mf2_t vs2, size_t vl) {
59+
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
60+
return __riscv_vfwmaccbf16_vv_f32m1_rm_mu(mask, vd, vs1, vs2, 5, vl);
61+
}
62+
63+
vfloat32m1_t test_vfwmaccbf16_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, __bf16 vs1, vbfloat16mf2_t vs2, size_t vl) {
64+
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
65+
return __riscv_vfwmaccbf16_vf_f32m1_rm_mu(mask, vd, vs1, vs2, 5, vl);
66+
}

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