[#1324] add support for platforms with non native 64 bit atomics

[elfenpiff]

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References

Closes #1324

[codecov]

Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 77.85%. Comparing base (03b09c5) to head (cbde9fe).
⚠️ Report is 60 commits behind head on main.

Additional details and impacted files

@@            Coverage Diff             @@
##             main    #1325      +/-   ##
==========================================
- Coverage   77.86%   77.85%   -0.02%     
==========================================
  Files         405      405              
  Lines       38759    38759              
  Branches     1256     1256              
==========================================
- Hits        30179    30175       -4     
- Misses       7547     7551       +4     
  Partials     1033     1033              

Flag	Coverage Δ
CPP	68.04% <ø> (ø)
Rust	77.70% <ø> (-0.02%)	⬇️

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Files with missing lines	Coverage Δ
iceoryx2-pal/concurrency-sync/src/atomic.rs	96.48% <ø> (ø)

... and 3 files with indirect coverage changes

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[elBoberido]

I strongly advice not to do this. All modern (newer than 30 years) CPU architectures not meant for microcontroller support 8 byte CAS also on 32 bit. For uCs, using a spin-lock will lead to deadlocks in common use cases, even if nothing goes wrong. For example, queues are often used to pass data from interrupt service routines to the main loop. iceoryx2 would be ideal for this use case. But with the spin-lock, this can deadlock when a subscriber takes samples in the main loop while a publisher publishes data in the ISR. The warning also does not give any hint that this can happen, because there are no processes on uCs. For anything that can run a process, we already support 8 byte CAS on 32 bit. But even for those use cases, as a user I have no clue what this means. I'm only using publish-subscribe and there is no warning about that, so I'm fine, right?