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Merge pull request #607 from okhsunrog/adding_eeprom
Added EEPROM support for L0/L1 series
2 parents 7eaf7e1 + e926d69 commit 665fa96

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-26
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4 files changed

+83
-26
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‎stm32-data-gen/src/memory.rs‎

Lines changed: 79 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -55,6 +55,14 @@ macro_rules! mem {
5555
access: Some(access(stringify!($access))),
5656
}
5757
};
58+
(@row $name:ident $addr:literal $size:literal bytes $access:ident) => {
59+
Mem {
60+
name: stringify!($name),
61+
address: $addr,
62+
size: $size,
63+
access: Some(access(stringify!($access))),
64+
}
65+
};
5866

5967
($( $name:ident{$($row:tt)*}),*) => {
6068
&[
@@ -246,33 +254,69 @@ static MEMS: RegexMap<&[&[Mem]]> = RegexMap::new(&[
246254
("STM32H7A..G", &[mem!(BANK_1 { 0x08000000 512 }, BANK_2 { 0x08100000 512 }, ITCM { 0x00000000 64 }, DTCM { 0x20000000 128 }, AXISRAM { 0x24000000 1024 }, AHBSRAM { 0x30000000 128 })]),
247255
("STM32H7B..B", &[mem!(BANK_1 { 0x08000000 128 }, ITCM { 0x00000000 64 }, DTCM { 0x20000000 128 }, AXISRAM { 0x24000000 1024 }, AHBSRAM { 0x30000000 128 })]),
248256
// L0
249-
("STM32L0...3", &[mem!(BANK_1 { 0x08000000 8 }, SRAM { 0x20000000 2 })]),
250-
("STM32L0...6", &[mem!(BANK_1 { 0x08000000 32 }, SRAM { 0x20000000 8 })]),
251-
("STM32L0...B", &[mem!(BANK_1 { 0x08000000 128 }, SRAM { 0x20000000 20 })]),
252-
("STM32L0...Z", &[mem!(BANK_1 { 0x08000000 192 }, SRAM { 0x20000000 20 })]),
253-
("STM32L0[12]..4", &[mem!(BANK_1 { 0x08000000 16 }, SRAM { 0x20000000 2 })]),
254-
("STM32L0[156]..8", &[mem!(BANK_1 { 0x08000000 64 }, SRAM { 0x20000000 8 })]),
255-
("STM32L0[34]..4", &[mem!(BANK_1 { 0x08000000 16 }, SRAM { 0x20000000 8 })]),
256-
("STM32L0[78]..8", &[mem!(BANK_1 { 0x08000000 64 }, SRAM { 0x20000000 20 })]),
257+
// L0x0
258+
("STM32L010.4", &[mem!(BANK_1 { 0x08000000 16 }, SRAM { 0x20000000 2 }, EEPROM { 0x08080000 128 bytes rw })]), // STM32L010F4, K4
259+
("STM32L010.6", &[mem!(BANK_1 { 0x08000000 32 }, SRAM { 0x20000000 8 }, EEPROM { 0x08080000 256 bytes rw })]), // STM32L010C6
260+
("STM32L010.8", &[mem!(BANK_1 { 0x08000000 64 }, SRAM { 0x20000000 8 }, EEPROM { 0x08080000 256 bytes rw })]), // STM32L010K8, R8
261+
("STM32L010.B", &[mem!(BANK_1 { 0x08000000 128 }, SRAM { 0x20000000 20 }, EEPROM { 0x08080000 512 bytes rw })]), // STM32L010RB
262+
// L0x1 Category 1
263+
("STM32L011.3", &[mem!(BANK_1 { 0x08000000 8 }, SRAM { 0x20000000 2 }, EEPROM { 0x08080000 512 bytes rw })]), // STM32L011D3, E3, F3, G3, K3
264+
("STM32L011.4", &[mem!(BANK_1 { 0x08000000 16 }, SRAM { 0x20000000 2 }, EEPROM { 0x08080000 512 bytes rw })]), // STM32L011D4, E4, F4, G4, K4
265+
("STM32L021.4", &[mem!(BANK_1 { 0x08000000 16 }, SRAM { 0x20000000 2 }, EEPROM { 0x08080000 512 bytes rw })]), // STM32L021D4, F4, G4, K4
266+
// L0x1 Category 2
267+
("STM32L031.4", &[mem!(BANK_1 { 0x08000000 16 }, SRAM { 0x20000000 8 }, EEPROM { 0x08080000 1024 bytes rw })]), // STM32L031C4, E4, F4, G4, K4
268+
("STM32L031.6", &[mem!(BANK_1 { 0x08000000 32 }, SRAM { 0x20000000 8 }, EEPROM { 0x08080000 1024 bytes rw })]), // STM32L031C6, E6, F6, G6, K6
269+
("STM32L041.4", &[mem!(BANK_1 { 0x08000000 16 }, SRAM { 0x20000000 8 }, EEPROM { 0x08080000 1024 bytes rw })]), // STM32L041C4
270+
("STM32L041.6", &[mem!(BANK_1 { 0x08000000 32 }, SRAM { 0x20000000 8 }, EEPROM { 0x08080000 1024 bytes rw })]), // STM32L041C6, E6, F6, G6, K6
271+
// L0x1, L0x2, L0x3 Category 3
272+
("STM32L051.6", &[mem!(BANK_1 { 0x08000000 32 }, SRAM { 0x20000000 8 }, EEPROM { 0x08080000 2048 bytes rw })]), // STM32L051C6, K6, R6, T6
273+
("STM32L051.8", &[mem!(BANK_1 { 0x08000000 64 }, SRAM { 0x20000000 8 }, EEPROM { 0x08080000 2048 bytes rw })]), // STM32L051C8, K8, R8, T8
274+
("STM32L052.6", &[mem!(BANK_1 { 0x08000000 32 }, SRAM { 0x20000000 8 }, EEPROM { 0x08080000 2048 bytes rw })]), // STM32L052C6, K6, R6, T6
275+
("STM32L052.8", &[mem!(BANK_1 { 0x08000000 64 }, SRAM { 0x20000000 8 }, EEPROM { 0x08080000 2048 bytes rw })]), // STM32L052C8, K8, R8, T8
276+
("STM32L053.6", &[mem!(BANK_1 { 0x08000000 32 }, SRAM { 0x20000000 8 }, EEPROM { 0x08080000 2048 bytes rw })]), // STM32L053C6, R6
277+
("STM32L053.8", &[mem!(BANK_1 { 0x08000000 64 }, SRAM { 0x20000000 8 }, EEPROM { 0x08080000 2048 bytes rw })]), // STM32L053C8, R8
278+
("STM32L062.8", &[mem!(BANK_1 { 0x08000000 64 }, SRAM { 0x20000000 8 }, EEPROM { 0x08080000 2048 bytes rw })]), // STM32L062C8, K8
279+
("STM32L063.8", &[mem!(BANK_1 { 0x08000000 64 }, SRAM { 0x20000000 8 }, EEPROM { 0x08080000 2048 bytes rw })]), // STM32L063C8, R8
280+
// L0x1, L0x2, L0x3 Category 5 (64KB Flash, only EEPROM bank 2)
281+
("STM32L071.8", &[mem!(BANK_1 { 0x08000000 64 }, SRAM { 0x20000000 20 }, EEPROM_BANK_2 { 0x08080C00 3072 bytes rw })]), // STM32L071C8, K8, V8
282+
("STM32L072.8", &[mem!(BANK_1 { 0x08000000 64 }, SRAM { 0x20000000 20 }, EEPROM_BANK_2 { 0x08080C00 3072 bytes rw })]), // STM32L072V8
283+
("STM32L073.8", &[mem!(BANK_1 { 0x08000000 64 }, SRAM { 0x20000000 20 }, EEPROM_BANK_2 { 0x08080C00 3072 bytes rw })]), // STM32L073V8
284+
("STM32L083.8", &[mem!(BANK_1 { 0x08000000 64 }, SRAM { 0x20000000 20 }, EEPROM_BANK_2 { 0x08080C00 3072 bytes rw })]), // STM32L083V8
285+
// L0x1, L0x2, L0x3 Category 5 (128KB and 192KB Flash, dual EEPROM banks)
286+
("STM32L071.B", &[mem!(BANK_1 { 0x08000000 128 }, SRAM { 0x20000000 20 }, EEPROM_BANK_1 { 0x08080000 3072 bytes rw }, EEPROM_BANK_2 { 0x08080C00 3072 bytes rw })]), // STM32L071CB, KB, RB, VB
287+
("STM32L071.Z", &[mem!(BANK_1 { 0x08000000 192 }, SRAM { 0x20000000 20 }, EEPROM_BANK_1 { 0x08080000 3072 bytes rw }, EEPROM_BANK_2 { 0x08080C00 3072 bytes rw })]), // STM32L071CZ, KZ, RZ, VZ
288+
("STM32L072.B", &[mem!(BANK_1 { 0x08000000 128 }, SRAM { 0x20000000 20 }, EEPROM_BANK_1 { 0x08080000 3072 bytes rw }, EEPROM_BANK_2 { 0x08080C00 3072 bytes rw })]), // STM32L072CB, KB, RB, VB
289+
("STM32L072.Z", &[mem!(BANK_1 { 0x08000000 192 }, SRAM { 0x20000000 20 }, EEPROM_BANK_1 { 0x08080000 3072 bytes rw }, EEPROM_BANK_2 { 0x08080C00 3072 bytes rw })]), // STM32L072CZ, KZ, RZ, VZ
290+
("STM32L073.B", &[mem!(BANK_1 { 0x08000000 128 }, SRAM { 0x20000000 20 }, EEPROM_BANK_1 { 0x08080000 3072 bytes rw }, EEPROM_BANK_2 { 0x08080C00 3072 bytes rw })]), // STM32L073CB, RB, VB
291+
("STM32L073.Z", &[mem!(BANK_1 { 0x08000000 192 }, SRAM { 0x20000000 20 }, EEPROM_BANK_1 { 0x08080000 3072 bytes rw }, EEPROM_BANK_2 { 0x08080C00 3072 bytes rw })]), // STM32L073CZ, RZ, VZ
292+
("STM32L081.B", &[mem!(BANK_1 { 0x08000000 128 }, SRAM { 0x20000000 20 }, EEPROM_BANK_1 { 0x08080000 3072 bytes rw }, EEPROM_BANK_2 { 0x08080C00 3072 bytes rw })]), // STM32L081CB
293+
("STM32L081.Z", &[mem!(BANK_1 { 0x08000000 192 }, SRAM { 0x20000000 20 }, EEPROM_BANK_1 { 0x08080000 3072 bytes rw }, EEPROM_BANK_2 { 0x08080C00 3072 bytes rw })]), // STM32L081CZ, KZ
294+
("STM32L082.B", &[mem!(BANK_1 { 0x08000000 128 }, SRAM { 0x20000000 20 }, EEPROM_BANK_1 { 0x08080000 3072 bytes rw }, EEPROM_BANK_2 { 0x08080C00 3072 bytes rw })]), // STM32L082KB
295+
("STM32L082.Z", &[mem!(BANK_1 { 0x08000000 192 }, SRAM { 0x20000000 20 }, EEPROM_BANK_1 { 0x08080000 3072 bytes rw }, EEPROM_BANK_2 { 0x08080C00 3072 bytes rw })]), // STM32L082CZ, KZ
296+
("STM32L083.B", &[mem!(BANK_1 { 0x08000000 128 }, SRAM { 0x20000000 20 }, EEPROM_BANK_1 { 0x08080000 3072 bytes rw }, EEPROM_BANK_2 { 0x08080C00 3072 bytes rw })]), // STM32L083CB, RB, VB
297+
("STM32L083.Z", &[mem!(BANK_1 { 0x08000000 192 }, SRAM { 0x20000000 20 }, EEPROM_BANK_1 { 0x08080000 3072 bytes rw }, EEPROM_BANK_2 { 0x08080C00 3072 bytes rw })]), // STM32L083CZ, RZ, VZ
257298
// L1
258-
("STM32L1...C..", &[mem!(BANK_1 { 0x08000000 256 }, SRAM { 0x20000000 32 })]),
259-
("STM32L1...D..", &[mem!(BANK_1 { 0x08000000 192 }, BANK_2 { 0x08030000 192 }, SRAM { 0x20000000 80 })]),
260-
("STM32L1...D", &[mem!(BANK_1 { 0x08000000 192 }, BANK_2 { 0x08030000 192 }, SRAM { 0x20000000 48 })]),
261-
("STM32L1...E", &[mem!(BANK_1 { 0x08000000 256 }, BANK_2 { 0x08040000 256 }, SRAM { 0x20000000 80 })]),
262-
("STM32L1[56]..C", &[mem!(BANK_1 { 0x08000000 256 }, SRAM { 0x20000000 32 })]),
263-
("STM32L10..6..", &[mem!(BANK_1 { 0x08000000 32 }, SRAM { 0x20000000 4 })]),
264-
("STM32L10..6", &[mem!(BANK_1 { 0x08000000 32 }, SRAM { 0x20000000 4 })]),
265-
("STM32L10..8..", &[mem!(BANK_1 { 0x08000000 64 }, SRAM { 0x20000000 8 })]),
266-
("STM32L10..8", &[mem!(BANK_1 { 0x08000000 64 }, SRAM { 0x20000000 8 })]),
267-
("STM32L10..B..", &[mem!(BANK_1 { 0x08000000 128 }, SRAM { 0x20000000 16 })]),
268-
("STM32L10..B", &[mem!(BANK_1 { 0x08000000 128 }, SRAM { 0x20000000 10 })]),
269-
("STM32L10..C", &[mem!(BANK_1 { 0x08000000 256 }, SRAM { 0x20000000 16 })]),
270-
("STM32L15..6..", &[mem!(BANK_1 { 0x08000000 32 }, SRAM { 0x20000000 16 })]),
271-
("STM32L15..6", &[mem!(BANK_1 { 0x08000000 32 }, SRAM { 0x20000000 10 })]),
272-
("STM32L15..8..", &[mem!(BANK_1 { 0x08000000 64 }, SRAM { 0x20000000 32 })]),
273-
("STM32L15..8", &[mem!(BANK_1 { 0x08000000 64 }, SRAM { 0x20000000 10 })]),
274-
("STM32L15..B..", &[mem!(BANK_1 { 0x08000000 128 }, SRAM { 0x20000000 32 })]),
275-
("STM32L15..B", &[mem!(BANK_1 { 0x08000000 128 }, SRAM { 0x20000000 16 })]),
299+
("STM32L1...C..", &[mem!(BANK_1 { 0x08000000 256 }, SRAM { 0x20000000 32 }, EEPROM { 0x08080000 8192 bytes rw })]), // Cat.3
300+
("STM32L1...D", &[mem!(BANK_1 { 0x08000000 192 }, BANK_2 { 0x08030000 192 }, SRAM { 0x20000000 48 }, EEPROM_BANK_1 { 0x08080000 6144 bytes rw }, EEPROM_BANK_2 { 0x08081800 6144 bytes rw })]), // Cat.4
301+
("STM32L1...D..", &[mem!(BANK_1 { 0x08000000 192 }, BANK_2 { 0x08030000 192 }, SRAM { 0x20000000 80 }, EEPROM_BANK_1 { 0x08080000 8192 bytes rw }, EEPROM_BANK_2 { 0x08082000 8192 bytes rw })]), // Cat.5/6 (e.g., STM32L151VD-X)
302+
("STM32L1...E", &[mem!(BANK_1 { 0x08000000 256 }, BANK_2 { 0x08040000 256 }, SRAM { 0x20000000 80 }, EEPROM_BANK_1 { 0x08080000 8192 bytes rw }, EEPROM_BANK_2 { 0x08082000 8192 bytes rw })]), // Cat.5/6
303+
("STM32L10..6..", &[mem!(BANK_1 { 0x08000000 32 }, SRAM { 0x20000000 4 }, EEPROM { 0x08080000 4096 bytes rw })]), // Cat.1/2 (STM32L100C6-A)
304+
("STM32L10..6", &[mem!(BANK_1 { 0x08000000 32 }, SRAM { 0x20000000 4 }, EEPROM { 0x08080000 4096 bytes rw })]), // Cat.1/2 (STM32L100C6)
305+
("STM32L10..8..", &[mem!(BANK_1 { 0x08000000 64 }, SRAM { 0x20000000 8 }, EEPROM { 0x08080000 4096 bytes rw })]), // Cat.1/2 (STM32L100R8-A)
306+
("STM32L10..8", &[mem!(BANK_1 { 0x08000000 64 }, SRAM { 0x20000000 8 }, EEPROM { 0x08080000 4096 bytes rw })]), // Cat.1/2 (STM32L100R8)
307+
("STM32L10..B..", &[mem!(BANK_1 { 0x08000000 128 }, SRAM { 0x20000000 16 }, EEPROM { 0x08080000 4096 bytes rw })]), // Cat.1/2 (STM32L100RB-A)
308+
("STM32L10..B", &[mem!(BANK_1 { 0x08000000 128 }, SRAM { 0x20000000 10 }, EEPROM { 0x08080000 4096 bytes rw })]), // Cat.1/2 (STM32L100RB)
309+
("STM32L10..C", &[mem!(BANK_1 { 0x08000000 256 }, SRAM { 0x20000000 16 }, EEPROM { 0x08080000 8192 bytes rw })]), // Cat.3 (STM32L100RC)
310+
("STM32L15..6..", &[mem!(BANK_1 { 0x08000000 32 }, SRAM { 0x20000000 16 }, EEPROM { 0x08080000 4096 bytes rw })]), // Cat.1/2 (STM32L151C6-A, etc.)
311+
("STM32L15..6", &[mem!(BANK_1 { 0x08000000 32 }, SRAM { 0x20000000 10 }, EEPROM { 0x08080000 4096 bytes rw })]), // Cat.1/2 (STM32L151C6, etc.)
312+
("STM32L15..8..", &[mem!(BANK_1 { 0x08000000 64 }, SRAM { 0x20000000 32 }, EEPROM { 0x08080000 4096 bytes rw })]), // Cat.1/2 (STM32L151C8-A, etc.)
313+
("STM32L15..8", &[mem!(BANK_1 { 0x08000000 64 }, SRAM { 0x20000000 10 }, EEPROM { 0x08080000 4096 bytes rw })]), // Cat.1/2 (STM32L151C8, etc.)
314+
("STM32L15..B..", &[mem!(BANK_1 { 0x08000000 128 }, SRAM { 0x20000000 32 }, EEPROM { 0x08080000 4096 bytes rw })]), // Cat.1/2 (STM32L151CB-A, etc.)
315+
("STM32L15..B", &[mem!(BANK_1 { 0x08000000 128 }, SRAM { 0x20000000 16 }, EEPROM { 0x08080000 4096 bytes rw })]), // Cat.1/2 (STM32L151CB, etc.)
316+
("STM32L15..C", &[mem!(BANK_1 { 0x08000000 256 }, SRAM { 0x20000000 32 }, EEPROM { 0x08080000 8192 bytes rw })]), // Cat.3
317+
("STM32L16..C", &[mem!(BANK_1 { 0x08000000 256 }, SRAM { 0x20000000 32 }, EEPROM { 0x08080000 8192 bytes rw })]), // Cat.3
318+
("STM32L16..D", &[mem!(BANK_1 { 0x08000000 384 }, SRAM { 0x20000000 48 }, EEPROM_BANK_1 { 0x08080000 6144 bytes rw }, EEPROM_BANK_2 { 0x08081800 6144 bytes rw })]), // Cat.4
319+
("STM32L16..E", &[mem!(BANK_1 { 0x08000000 512 }, SRAM { 0x20000000 80 }, EEPROM_BANK_1 { 0x08080000 8192 bytes rw }, EEPROM_BANK_2 { 0x08082000 8192 bytes rw })]), // Cat.5/6
276320
// L4
277321
("STM32L4...8", &[mem!(BANK_1 { 0x08000000 64 }, SRAM { 0x20000000 32 }, SRAM2 { 0x20008000 8 }, SRAM2_ICODE { 0x10000000 8 })]),
278322
("STM32L4[12]..B", &[mem!(BANK_1 { 0x08000000 128 }, SRAM { 0x20000000 32 }, SRAM2 { 0x20008000 8 }, SRAM2_ICODE { 0x10000000 8 })]),
@@ -485,6 +529,15 @@ pub fn get(chip: &str) -> Vec<Vec<Memory>> {
485529
}),
486530
access: mem.access,
487531
});
532+
} else if mem.name.starts_with("EEPROM") {
533+
res.push(Memory {
534+
name: mem.name.to_string(),
535+
address: mem.address,
536+
size: mem.size,
537+
kind: memory::Kind::Eeprom,
538+
settings: None,
539+
access: mem.access,
540+
});
488541
} else {
489542
let mut kind = memory::Kind::Ram;
490543
if mem.name.contains("FLASH") || mem.name.contains("AXIICP") {

‎stm32-data-serde/src/lib.rs‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -64,6 +64,7 @@ pub mod chip {
6464
pub enum Kind {
6565
Flash,
6666
Ram,
67+
Eeprom,
6768
}
6869

6970
#[derive(Clone, Debug, Eq, PartialEq, Hash, PartialOrd, Ord, Serialize, Deserialize)]

‎stm32-metapac-gen/res/src/metadata.rs‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -154,6 +154,7 @@ pub struct FlashSettings {
154154
pub enum MemoryRegionKind {
155155
Flash,
156156
Ram,
157+
Eeprom,
157158
}
158159

159160
#[derive(Debug, Eq, PartialEq, Clone)]

‎stm32-metapac-gen/src/data.rs‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -330,6 +330,8 @@ pub enum MemoryRegionKind {
330330
Flash,
331331
#[serde(rename = "ram")]
332332
Ram,
333+
#[serde(rename = "eeprom")]
334+
Eeprom,
333335
}
334336

335337
#[derive(Debug, Eq, PartialEq, Clone, Deserialize)]

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