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9 changes: 5 additions & 4 deletions liteeth/phy/rmii.py
Original file line number Diff line number Diff line change
Expand Up @@ -109,14 +109,15 @@ def __init__(self, clock_pads, pads, refclk_cd,

# Else use refclk_cd as RMII reference clock (provided by user design).
else:
self.comb += self.cd_eth_rx.clk.eq(ClockSignal(refclk_cd))
self.comb += self.cd_eth_tx.clk.eq(ClockSignal(refclk_cd))
clk_signal = ClockSignal(refclk_cd)
self.comb += self.cd_eth_rx.clk.eq(clk_signal)
self.comb += self.cd_eth_tx.clk.eq(clk_signal)
# Drive clock_pads if provided.
if clock_pads is not None:
if with_refclk_ddr_output:
self.specials += DDROutput(i1=0, i2=1, o=clock_pads.ref_clk, clk=ClockSignal("eth_tx"))
self.specials += DDROutput(i1=0, i2=1, o=clock_pads.ref_clk, clk=clk_signal)
else:
self.comb += clock_pads.ref_clk.eq(~ClockSignal("eth_tx")) # CHEKCME: Keep Invert?
self.comb += clock_pads.ref_clk.eq(~clk_signal) # CHEKCME: Keep Invert?

# Reset
self.reset = reset = Signal()
Expand Down