Add jumbo frame support & fix Stream2UDPTX freeze-up

.gitignore

@@ -44,6 +44,7 @@ nosetests.xml
 coverage.xml
 *,cover
 .hypothesis/
+sim.vcd
 
 # Translations
 *.mo

liteeth/common.py

@@ -18,12 +18,12 @@
 
 # Ethernet Constants -------------------------------------------------------------------------------
 
-eth_mtu              = 1530
+eth_mtu_default      = 1530
+eth_mtu_jumboframe   = 9022
 eth_min_frame_length = 64
 eth_fcs_length       = 4
 eth_interpacket_gap  = 12
 eth_preamble         = 0xd555555555555555
-buffer_depth         = 2**log2_int(eth_mtu, need_pow2=False)
 
 ethernet_type_ip     = 0x800
 ethernet_type_arp    = 0x806

liteeth/core/__init__.py

@@ -27,6 +27,7 @@ def __init__(self, phy, mac_address, ip_address, clk_freq, arp_entries=1, dw=8,
         rx_cdc_buffered   = True,
         interface         = "crossbar",
         endianness        = "big",
+        eth_mtu           = eth_mtu_default,
     ):
         # Parameters.
         # -----------
@@ -45,7 +46,8 @@ def __init__(self, phy, mac_address, ip_address, clk_freq, arp_entries=1, dw=8,
             tx_cdc_depth      = tx_cdc_depth,
             tx_cdc_buffered   = tx_cdc_buffered,
             rx_cdc_depth      = rx_cdc_depth,
-            rx_cdc_buffered   = rx_cdc_buffered
+            rx_cdc_buffered   = rx_cdc_buffered,
+            eth_mtu           = eth_mtu,
         )
 
         # ARP.
@@ -92,6 +94,7 @@ def __init__(self, phy, mac_address, ip_address, clk_freq, arp_entries=1, dw=8,
         rx_cdc_buffered   = True,
         interface         = "crossbar",
         endianness        = "big",
+        eth_mtu           = eth_mtu_default,
     ):
         # Parameters.
         # -----------
@@ -116,6 +119,7 @@ def __init__(self, phy, mac_address, ip_address, clk_freq, arp_entries=1, dw=8,
             tx_cdc_buffered   = tx_cdc_buffered,
             rx_cdc_depth      = rx_cdc_depth,
             rx_cdc_buffered   = rx_cdc_buffered,
+            eth_mtu           = eth_mtu,
         )
         # UDP.
         # ----

liteeth/frontend/stream.py

@@ -44,7 +44,7 @@ def __init__(self, ip_address=0, udp_port=0, data_width=8, fifo_depth=None, with
             self.comb += sink.connect(fifo.sink)
 
             self.fsm = fsm = ResetInserter()(FSM(reset_state="IDLE"))
-            self.comb += fsm.reset.eq(~self.enable)
+            self.comb += fsm.reset.eq(~self.enable & ~source.valid)
 
             fsm.act("IDLE",
                 NextValue(counter, 0),

liteeth/mac/__init__.py

@@ -31,6 +31,7 @@ def __init__(self, phy, dw,
         tx_cdc_buffered    = False,
         rx_cdc_depth       = 32,
         rx_cdc_buffered    = False,
+        eth_mtu            = eth_mtu_default,
     ):
         assert dw%8 == 0
         assert interface  in ["crossbar", "wishbone", "hybrid"]
@@ -47,6 +48,7 @@ def __init__(self, phy, dw,
             tx_cdc_buffered   = tx_cdc_buffered,
             rx_cdc_depth      = rx_cdc_depth,
             rx_cdc_buffered   = rx_cdc_buffered,
+            eth_mtu           = eth_mtu,
         )
         self.csrs = []
 
@@ -76,6 +78,7 @@ def __init__(self, phy, dw,
                 ntxslots   = ntxslots, txslots_write_only = txslots_write_only,
                 endianness = endianness,
                 timestamp  = timestamp,
+                eth_mtu    = eth_mtu,
             )
             if full_memory_we:
                 wishbone_interface = self.apply_full_memory_we(wishbone_interface)

liteeth/mac/core.py

@@ -46,6 +46,7 @@ def __init__(self, phy, dw,
         tx_cdc_buffered   = False,
         rx_cdc_depth      = 32,
         rx_cdc_buffered   = False,
+        eth_mtu           = eth_mtu_default,
         ):
 
         # Endpoints.
@@ -247,7 +248,7 @@ def add_crc(self):
 
             def add_padding(self):
                 """Add padding checker for minimum frame length."""
-                rx_padding = padding.LiteEthMACPaddingChecker(datapath_dw, (eth_min_frame_length - eth_fcs_length))
+                rx_padding = padding.LiteEthMACPaddingChecker(datapath_dw, (eth_min_frame_length - eth_fcs_length), eth_mtu=eth_mtu)
                 rx_padding = ClockDomainsRenamer(cd_rx)(rx_padding)
                 self.submodules += rx_padding
                 self.pipeline.append(rx_padding)

liteeth/mac/padding.py

@@ -69,7 +69,7 @@ def __init__(self, dw, padding):
 # MAC Padding Checker ------------------------------------------------------------------------------
 
 class LiteEthMACPaddingChecker(Module):
-    def __init__(self, dw, packet_min_length):
+    def __init__(self, dw, packet_min_length, eth_mtu=eth_mtu_default):
         self.sink   = sink   = stream.Endpoint(eth_phy_description(dw))
         self.source = source = stream.Endpoint(eth_phy_description(dw))
 

liteeth/mac/sram.py

@@ -19,13 +19,14 @@
 # MAC SRAM Writer ----------------------------------------------------------------------------------
 
 class LiteEthMACSRAMWriter(LiteXModule):
-    def __init__(self, dw, depth, nslots=2, endianness="big", timestamp=None):
+    def __init__(self, dw, depth, nslots=2, endianness="big", timestamp=None, eth_mtu=eth_mtu_default):
         # Endpoint / Signals.
         self.sink      = sink = stream.Endpoint(eth_phy_description(dw))
         self.crc_error = Signal()
 
         # Parameters Check / Compute.
         assert dw in [8, 16, 32, 64]
+        self.eth_mtu = eth_mtu
         slotbits   = max(int(math.log2(nslots)), 1)
         lengthbits = bits_for(depth * dw//8)
 
@@ -81,7 +82,7 @@ def __init__(self, dw, depth, nslots=2, endianness="big", timestamp=None):
                 If(stat_fifo.sink.ready,
                     write.eq(1),
                     NextValue(length, length + length_inc),
-                    If(length >= eth_mtu,
+                    If(length >= self.eth_mtu,
                          NextState("DISCARD-REMAINING")
                     ),
                     If(sink.last,
@@ -304,8 +305,8 @@ def __init__(self, dw, depth, nslots=2, endianness="big", timestamp=None):
 # MAC SRAM -----------------------------------------------------------------------------------------
 
 class LiteEthMACSRAM(LiteXModule):
-    def __init__(self, dw, depth, nrxslots, ntxslots, endianness, timestamp=None):
-        self.writer = LiteEthMACSRAMWriter(dw, depth, nrxslots, endianness, timestamp)
+    def __init__(self, dw, depth, nrxslots, ntxslots, endianness, timestamp=None, eth_mtu=eth_mtu_default):
+        self.writer = LiteEthMACSRAMWriter(dw, depth, nrxslots, endianness, timestamp, eth_mtu=eth_mtu)
         self.reader = LiteEthMACSRAMReader(dw, depth, ntxslots, endianness, timestamp)
         self.ev     = SharedIRQ(self.writer.ev, self.reader.ev)
         self.sink, self.source = self.writer.sink, self.reader.source

liteeth/mac/wishbone.py

@@ -21,6 +21,7 @@ class LiteEthMACWishboneInterface(LiteXModule):
     def __init__(self, dw, nrxslots=2, ntxslots=2, endianness="big", timestamp=None,
         rxslots_read_only  = True,
         txslots_write_only = False,
+        eth_mtu            = eth_mtu_default,
     ):
         self.sink   = stream.Endpoint(eth_phy_description(dw))
         self.source = stream.Endpoint(eth_phy_description(dw))
@@ -31,8 +32,9 @@ def __init__(self, dw, nrxslots=2, ntxslots=2, endianness="big", timestamp=None,
 
         # Storage in SRAM.
         # ----------------
+        self.eth_mtu = eth_mtu
         sram_depth = math.ceil(eth_mtu/(dw//8))
-        self.sram = sram.LiteEthMACSRAM(dw, sram_depth, nrxslots, ntxslots, endianness, timestamp)
+        self.sram = sram.LiteEthMACSRAM(dw, sram_depth, nrxslots, ntxslots, endianness, timestamp, eth_mtu=eth_mtu)
         self.comb += [
             self.sink.connect(self.sram.sink),
             self.sram.source.connect(self.source),
@@ -70,7 +72,7 @@ def _expose_wishbone_sram_interfaces(self, bus, dw, mems, nslots, read_only, wri
 
         # Expose SRAMs on Bus.
         wb_slaves      = []
-        sram_depth     = math.ceil(eth_mtu/(dw//8))
+        sram_depth     = math.ceil(self.eth_mtu/(dw//8))
         decoderoffset  = log2_int(sram_depth, need_pow2=False)
         decoderbits    = max(log2_int(len(wb_sram_ifs)), 1)
         for n, wb_sram_if in enumerate(wb_sram_ifs):

test/test_arp.py

@@ -25,12 +25,12 @@
 # DUT ----------------------------------------------------------------------------------------------
 
 class DUT(LiteXModule):
-    def __init__(self):
+    def __init__(self, eth_mtu=eth_mtu_default):
         self.phy_model = phy.PHY(8, debug=False)
         self.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False)
         self.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False)
 
-        self.mac = LiteEthMAC(self.phy_model, dw=8, with_preamble_crc=True)
+        self.mac = LiteEthMAC(self.phy_model, dw=8, with_preamble_crc=True, eth_mtu=eth_mtu)
         self.arp = LiteEthARP(self.mac, mac_address, ip_address, 100000)
 
 # Genrator -----------------------------------------------------------------------------------------
@@ -50,15 +50,17 @@ def main_generator(dut):
 
 class TestARP(unittest.TestCase):
     def test(self):
-        dut = DUT()
-        generators = {
-            "sys"    : [main_generator(dut)],
-            "eth_tx" : [dut.phy_model.phy_sink.generator(), dut.phy_model.generator()],
-            "eth_rx" : [dut.phy_model.phy_source.generator()],
-        }
-        clocks = {
-            "sys"    : 10,
-            "eth_rx" : 10,
-            "eth_tx" : 10,
-        }
-        run_simulation(dut, generators, clocks, vcd_name="sim.vcd")
+        for mtu in [eth_mtu_default, eth_mtu_jumboframe]:
+            with self.subTest(eth_mtu=mtu):
+                dut = DUT(eth_mtu=mtu)
+                generators = {
+                    "sys"    : [main_generator(dut)],
+                    "eth_tx" : [dut.phy_model.phy_sink.generator(), dut.phy_model.generator()],
+                    "eth_rx" : [dut.phy_model.phy_source.generator()],
+                }
+                clocks = {
+                    "sys"    : 10,
+                    "eth_rx" : 10,
+                    "eth_tx" : 10,
+                }
+                run_simulation(dut, generators, clocks, vcd_name="sim.vcd")

test/test_etherbone.py

@@ -27,15 +27,15 @@
 # DUT ----------------------------------------------------------------------------------------------
 
 class DUT(LiteXModule):
-    def __init__(self):
+    def __init__(self, eth_mtu=eth_mtu_default):
         self.phy_model       = phy.PHY(8, debug=False)
         self.mac_model       = mac.MAC(self.phy_model, debug=False, loopback=False)
         self.arp_model       = arp.ARP(self.mac_model, mac_address, ip_address, debug=False)
         self.ip_model        = ip.IP(self.mac_model, mac_address, ip_address, debug=False, loopback=False)
         self.udp_model       = udp.UDP(self.ip_model, ip_address, debug=False, loopback=False)
         self.etherbone_model = etherbone.Etherbone(self.udp_model, debug=False)
 
-        self.core      = LiteEthUDPIPCore(self.phy_model, mac_address, ip_address, 100000)
+        self.core      = LiteEthUDPIPCore(self.phy_model, mac_address, ip_address, 100000, eth_mtu=eth_mtu)
         self.etherbone = LiteEthEtherbone(self.core.udp, 0x1234)
 
         self.sram         = wishbone.SRAM(1024)

test/test_icmp.py

@@ -30,14 +30,14 @@
 # DUT ----------------------------------------------------------------------------------------------
 
 class DUT(LiteXModule):
-    def __init__(self):
+    def __init__(self, eth_mtu=eth_mtu_default):
         self.phy_model  = phy.PHY(8, debug=True)
         self.mac_model  = mac.MAC(self.phy_model, debug=True, loopback=False)
         self.arp_model  = arp.ARP(self.mac_model, mac_address, ip_address, debug=True)
         self.ip_model   = ip.IP(self.mac_model, mac_address, ip_address, debug=True, loopback=False)
         self.icmp_model = icmp.ICMP(self.ip_model, ip_address, debug=True)
 
-        self.ip = LiteEthIPCore(self.phy_model, mac_address, ip_address, 100000)
+        self.ip = LiteEthIPCore(self.phy_model, mac_address, ip_address, 100000, eth_mtu=eth_mtu)
 
 # Generator ----------------------------------------------------------------------------------------
 
@@ -57,15 +57,17 @@ def main_generator(dut):
 
 class TestICMP(unittest.TestCase):
     def test(self):
-        dut = DUT()
-        generators = {
-            "sys"    : [main_generator(dut)],
-            "eth_tx" : [dut.phy_model.phy_sink.generator(), dut.phy_model.generator()],
-            "eth_rx" : [dut.phy_model.phy_source.generator()],
-        }
-        clocks = {
-            "sys":    10,
-            "eth_rx": 10,
-            "eth_tx": 10,
-        }
-        run_simulation(dut, generators, clocks, vcd_name="sim.vcd")
+        for mtu in [eth_mtu_default, eth_mtu_jumboframe]:
+            with self.subTest(eth_mtu=mtu):
+                dut = DUT(eth_mtu=mtu)
+                generators = {
+                    "sys"    : [main_generator(dut)],
+                    "eth_tx" : [dut.phy_model.phy_sink.generator(), dut.phy_model.generator()],
+                    "eth_rx" : [dut.phy_model.phy_source.generator()],
+                }
+                clocks = {
+                    "sys":    10,
+                    "eth_rx": 10,
+                    "eth_tx": 10,
+                }
+                run_simulation(dut, generators, clocks, vcd_name="sim.vcd")

test/test_ip.py

@@ -26,13 +26,13 @@
 # DUT ----------------------------------------------------------------------------------------------
 
 class DUT(LiteXModule):
-    def __init__(self):
+    def __init__(self, eth_mtu=eth_mtu_default):
         self.phy_model = phy.PHY(8, debug=False)
         self.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False)
         self.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False)
         self.ip_model  = ip.IP(self.mac_model, mac_address, ip_address, debug=False, loopback=True)
 
-        self.ip = LiteEthIPCore(self.phy_model, mac_address, ip_address, 100000)
+        self.ip = LiteEthIPCore(self.phy_model, mac_address, ip_address, 100000, eth_mtu=eth_mtu)
         self.ip_port = self.ip.ip.crossbar.get_port(udp_protocol)
 
 # Generator ----------------------------------------------------------------------------------------
@@ -53,15 +53,17 @@ def main_generator(dut):
 
 class TestIP(unittest.TestCase):
     def test(self):
-        dut = DUT()
-        generators = {
-            "sys"    : [main_generator(dut)],
-            "eth_tx" : [dut.phy_model.phy_sink.generator(), dut.phy_model.generator()],
-            "eth_rx" : [dut.phy_model.phy_source.generator()],
-        }
-        clocks = {
-            "sys"    : 10,
-            "eth_rx" : 10,
-            "eth_tx" : 10,
-        }
-        run_simulation(dut, generators, clocks, vcd_name="sim.vcd")
+        for mtu in [eth_mtu_default, eth_mtu_jumboframe]:
+            with self.subTest(eth_mtu=mtu):
+                dut = DUT(eth_mtu=mtu)
+                generators = {
+                    "sys"    : [main_generator(dut)],
+                    "eth_tx" : [dut.phy_model.phy_sink.generator(), dut.phy_model.generator()],
+                    "eth_rx" : [dut.phy_model.phy_source.generator()],
+                }
+                clocks = {
+                    "sys"    : 10,
+                    "eth_rx" : 10,
+                    "eth_tx" : 10,
+                }
+                run_simulation(dut, generators, clocks, vcd_name="sim.vcd")