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Initial UART support
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-10
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6 files changed

+70
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‎esp-hal/README.md‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -105,7 +105,7 @@ For help getting started with this HAL, please refer to [The Rust on ESP Book] a
105105
| Timers | ⚒️ | ⚒️ | ⚒️ | ⚒️ | ⚒️ | ⚒️ | ⚒️ | ⚒️ | ⚒️ |
106106
| Touch | ⚒️ | | | [❌][5164] [^1] | | | | [❌][1905] [^1] | [❌][1905] [^1] |
107107
| TWAI / CAN / CANFD | ⚒️ | | ⚒️ | [❌][5163] [^1] | ⚒️ | | ⚒️ | ⚒️ | ⚒️ |
108-
| UART | ✔️ | ✔️ | ✔️ | ✔️ | ✔️ | | ✔️ | ✔️ | ✔️ |
108+
| UART | ✔️ | ✔️ | ✔️ | ✔️ | ✔️ | ✔️ | ✔️ | ✔️ | ✔️ |
109109
| UHCI | ❌ | | ⚒️ | ⚒️ | ⚒️ | | ⚒️ | ❌ | ⚒️ |
110110
| ULP (FSM) | ⚒️ | | | | | | | ⚒️ | ⚒️ |
111111
| ULP (RISC-V) | | | | [❌][5160] [^1] | ⚒️ | | | ⚒️ | ⚒️ |

‎esp-hal/src/uart/mod.rs‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1103,7 +1103,7 @@ impl<'d> UartRx<'d, Async> {
11031103
}
11041104

11051105
cfg_if::cfg_if! {
1106-
if #[cfg(any(esp32c5, esp32c6, esp32h2))] {
1106+
if #[cfg(any(esp32c5, esp32c6, esp32c61, esp32h2))] {
11071107
let reg_en = self.regs().tout_conf();
11081108
} else {
11091109
let reg_en = self.regs().conf1();
@@ -3309,7 +3309,7 @@ impl Info {
33093309
cfg_if::cfg_if! {
33103310
if #[cfg(esp32)] {
33113311
let reg_thrhd = register_block.conf1();
3312-
} else if #[cfg(any(esp32c5, esp32c6, esp32h2))] {
3312+
} else if #[cfg(any(esp32c5, esp32c6, esp32c61, esp32h2))] {
33133313
let reg_thrhd = register_block.tout_conf();
33143314
} else {
33153315
let reg_thrhd = register_block.mem_conf();
@@ -3319,7 +3319,7 @@ impl Info {
33193319
}
33203320

33213321
cfg_if::cfg_if! {
3322-
if #[cfg(any(esp32c5, esp32c6, esp32h2))] {
3322+
if #[cfg(any(esp32c5, esp32c6, esp32c61, esp32h2))] {
33233323
let reg_en = register_block.tout_conf();
33243324
} else {
33253325
let reg_en = register_block.conf1();
@@ -3462,7 +3462,7 @@ impl Info {
34623462
xoff_threshold,
34633463
} => {
34643464
cfg_if::cfg_if! {
3465-
if #[cfg(any(esp32c5, esp32c6, esp32h2))] {
3465+
if #[cfg(any(esp32c5, esp32c6, esp32c61, esp32h2))] {
34663466
self.regs().swfc_conf0().modify(|_, w| w.xonoff_del().set_bit().sw_flow_con_en().set_bit());
34673467
self.regs().swfc_conf1().modify(|_, w| unsafe { w.xon_threshold().bits(xon_threshold).xoff_threshold().bits(xoff_threshold)});
34683468
self.regs().swfc_conf0().modify(|_, w| unsafe { w.xon_char().bits(xon_char).xoff_char().bits(xoff_char) });
@@ -3481,7 +3481,7 @@ impl Info {
34813481
}
34823482
SwFlowControl::Disabled => {
34833483
cfg_if::cfg_if! {
3484-
if #[cfg(any(esp32c5, esp32c6, esp32h2))] {
3484+
if #[cfg(any(esp32c5, esp32c6, esp32c61, esp32h2))] {
34853485
let reg = self.regs().swfc_conf0();
34863486
} else {
34873487
let reg = self.regs().flow_conf();
@@ -3511,7 +3511,7 @@ impl Info {
35113511
cfg_if::cfg_if! {
35123512
if #[cfg(esp32)] {
35133513
self.regs().conf1().modify(|_, w| unsafe { w.rx_flow_thrhd().bits(threshold) });
3514-
} else if #[cfg(any(esp32c5, esp32c6, esp32h2))] {
3514+
} else if #[cfg(any(esp32c5, esp32c6, esp32c61, esp32h2))] {
35153515
self.regs().hwfc_conf().modify(|_, w| unsafe { w.rx_flow_thrhd().bits(threshold) });
35163516
} else {
35173517
self.regs().mem_conf().modify(|_, w| unsafe { w.rx_flow_thrhd().bits(threshold as u16) });
@@ -3520,7 +3520,7 @@ impl Info {
35203520
}
35213521

35223522
cfg_if::cfg_if! {
3523-
if #[cfg(any(esp32c5, esp32c6, esp32h2))] {
3523+
if #[cfg(any(esp32c5, esp32c6, esp32c61, esp32h2))] {
35243524
self.regs().hwfc_conf().modify(|_, w| {
35253525
w.rx_flow_en().bit(enable)
35263526
});

‎esp-metadata-generated/src/_build_script_utils.rs‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3028,8 +3028,11 @@ impl Chip {
30283028
"soc_driver_supported",
30293029
"systimer_driver_supported",
30303030
"timergroup_driver_supported",
3031+
"uart_driver_supported",
30313032
"timergroup_timg0",
30323033
"timergroup_timg1",
3034+
"uart_uart0",
3035+
"uart_uart1",
30333036
"gpio_gpio_function=\"1\"",
30343037
"gpio_constant_0_input=\"96\"",
30353038
"gpio_constant_1_input=\"64\"",
@@ -3070,6 +3073,8 @@ impl Chip {
30703073
"has_dram2_uninit_region",
30713074
"timergroup_timg_has_divcnt_rst",
30723075
"timergroup_rc_fast_calibration_is_set",
3076+
"uart_ram_size=\"128\"",
3077+
"uart_peripheral_controls_mem_clk",
30733078
],
30743079
cfgs: &[
30753080
"cargo:rustc-cfg=esp32c61",
@@ -3133,8 +3138,11 @@ impl Chip {
31333138
"cargo:rustc-cfg=soc_driver_supported",
31343139
"cargo:rustc-cfg=systimer_driver_supported",
31353140
"cargo:rustc-cfg=timergroup_driver_supported",
3141+
"cargo:rustc-cfg=uart_driver_supported",
31363142
"cargo:rustc-cfg=timergroup_timg0",
31373143
"cargo:rustc-cfg=timergroup_timg1",
3144+
"cargo:rustc-cfg=uart_uart0",
3145+
"cargo:rustc-cfg=uart_uart1",
31383146
"cargo:rustc-cfg=gpio_gpio_function=\"1\"",
31393147
"cargo:rustc-cfg=gpio_constant_0_input=\"96\"",
31403148
"cargo:rustc-cfg=gpio_constant_1_input=\"64\"",
@@ -3175,6 +3183,8 @@ impl Chip {
31753183
"cargo:rustc-cfg=has_dram2_uninit_region",
31763184
"cargo:rustc-cfg=timergroup_timg_has_divcnt_rst",
31773185
"cargo:rustc-cfg=timergroup_rc_fast_calibration_is_set",
3186+
"cargo:rustc-cfg=uart_ram_size=\"128\"",
3187+
"cargo:rustc-cfg=uart_peripheral_controls_mem_clk",
31783188
],
31793189
memory_layout: &MemoryLayout {
31803190
regions: &[

‎esp-metadata-generated/src/_generated_esp32c61.rs‎

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -151,6 +151,18 @@ macro_rules! property {
151151
("timergroup.timg_has_divcnt_rst") => {
152152
true
153153
};
154+
("uart.ram_size") => {
155+
128
156+
};
157+
("uart.ram_size", str) => {
158+
stringify!(128)
159+
};
160+
("uart.peripheral_controls_mem_clk") => {
161+
true
162+
};
163+
("uart.has_sclk_divider") => {
164+
false
165+
};
154166
}
155167
#[macro_export]
156168
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
@@ -2054,6 +2066,35 @@ macro_rules! memory_range {
20542066
"65536"
20552067
};
20562068
}
2069+
/// This macro can be used to generate code for each peripheral instance of the UART driver.
2070+
///
2071+
/// For an explanation on the general syntax, as well as usage of individual/repeated
2072+
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
2073+
///
2074+
/// This macro has one option for its "Individual matcher" case:
2075+
///
2076+
/// Syntax: `($id:literal, $instance:ident, $sys:ident, $rx:ident, $tx:ident, $cts:ident,
2077+
/// $rts:ident)`
2078+
///
2079+
/// Macro fragments:
2080+
///
2081+
/// - `$id`: the index of the UART instance
2082+
/// - `$instance`: the name of the UART instance
2083+
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
2084+
/// - `$rx`, `$tx`, `$cts`, `$rts`: signal names.
2085+
///
2086+
/// Example data: `(0, UART0, Uart0, U0RXD, U0TXD, U0CTS, U0RTS)`
2087+
#[macro_export]
2088+
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
2089+
macro_rules! for_each_uart {
2090+
($($pattern:tt => $code:tt;)*) => {
2091+
macro_rules! _for_each_inner_uart { $(($pattern) => $code;)* ($other : tt) => {}
2092+
} _for_each_inner_uart!((0, UART0, Uart0, U0RXD, U0TXD, U0CTS, U0RTS));
2093+
_for_each_inner_uart!((1, UART1, Uart1, U1RXD, U1TXD, U1CTS, U1RTS));
2094+
_for_each_inner_uart!((all(0, UART0, Uart0, U0RXD, U0TXD, U0CTS, U0RTS), (1,
2095+
UART1, Uart1, U1RXD, U1TXD, U1CTS, U1RTS)));
2096+
};
2097+
}
20572098
#[macro_export]
20582099
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
20592100
macro_rules! for_each_peripheral {

‎esp-metadata/devices/esp32c61.toml‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -342,3 +342,12 @@ output_signals = [
342342
support_status = "partial"
343343
trng_supported = false # TODO
344344
apb_cycle_wait_num = 16 # TODO
345+
346+
[device.uart]
347+
support_status = "supported"
348+
instances = [
349+
{ name = "uart0", sys_instance = "Uart0", tx = "U0TXD", rx = "U0RXD", cts = "U0CTS", rts = "U0RTS" },
350+
{ name = "uart1", sys_instance = "Uart1", tx = "U1TXD", rx = "U1RXD", cts = "U1CTS", rts = "U1RTS" },
351+
]
352+
ram_size = 128
353+
peripheral_controls_mem_clk = true

‎hil-test/src/bin/uart.rs‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
//! UART Test
22
3-
//% CHIPS: esp32 esp32c2 esp32c3 esp32c5 esp32c6 esp32h2 esp32s2 esp32s3
3+
//% CHIPS: esp32 esp32c2 esp32c3 esp32c5 esp32c6 esp32c61 esp32h2 esp32s2 esp32s3
44
//% FEATURES: unstable embassy
55

66
#![no_std]
@@ -171,7 +171,7 @@ mod tests {
171171
cfg_if::cfg_if! {
172172
if #[cfg(esp32c2)] {
173173
let fastest_clock_source = ClockSource::PllF40m;
174-
} else if #[cfg(any(esp32c5, esp32c6))] {
174+
} else if #[cfg(any(esp32c5, esp32c6, esp32c61))] {
175175
let fastest_clock_source = ClockSource::PllF80m;
176176
} else if #[cfg(esp32h2)] {
177177
let fastest_clock_source = ClockSource::PllF48m;

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