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reserved_for_rom_seg : ORIGIN = 0x3FFAE000, len = 8k /* SRAM2; reserved for usage by the ROM */
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dram_seg ( RW ) : ORIGIN = 0x3FFB0000 + RESERVE_DRAM, len = 176k - RESERVE_DRAM /* SRAM2+1; first 64kB used by BT if enable */
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-
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/*
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/*
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* The following values come from the heap allocator in esp-idf: https://github.com/espressif/esp-idf/blob/ab63aaa4a24a05904da2862d627f3987ecbeafd0/components/heap/port/esp32/memory_layout.c#L137-L157
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* The segment dram2_seg after the rom data space is not mentioned in the esp32 linker scripts in esp-idf, instead the space after is used as heap space.
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* It seems not all rom data space is reserved, but only "core"/"important" ROM functions that may be called after booting from ROM.
@@ -30,15 +30,15 @@ MEMORY
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/*
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* The following values are derived from the __stack and _stack_sentry values from ROM.
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* They represent the stacks used for each core setup by ROM code. In theory both of these
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* They represent the stacks used for each core setup by ROM code. In theory both of these
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* can be reclaimed once both cores are running, but for now we play it safe and reserve them both.
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*/
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reserved_rom_stack_pro : ORIGIN = 0x3ffe1320, len = 11264
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reserved_rom_stack_app : ORIGIN = 0x3ffe5230, len = 11264
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dram2_seg : ORIGIN = 0x3ffe7e30, len = 98767/* the rest of DRAM after the rom data segments and rom stacks in the middle */
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-
/* external flash
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/* external flash
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The 0x20 offset is a convenience for the app binary image generation.
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Flash cache has 64KB pages. The .bin file which is flashed to the chip
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has a 0x18 byte file header, and each segment has a 0x08 byte segment
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