Guard against an MMU table with no trailing empty entries

Previously the call to cache_dbus_mmu_set would have likely failed
instead. This is more explicit.

Author: EliteTK

esp-hal/src/soc/esp32s3/mmu.rs

@@ -7,10 +7,10 @@ const DBUS_VADDR_BASE: u32 = 0x3C000000;
 const DR_REG_MMU_TABLE: u32 = 0x600C5000;
 const ENTRY_INVALID: u32 = 1 << 14;
 const ICACHE_MMU_SIZE: usize = 0x800;
-const TABLE_SIZE: usize = ICACHE_MMU_SIZE / core::mem::size_of::<u32>();
 
 pub(super) const ENTRY_ACCESS_SPIRAM: u32 = 1 << 15;
 pub(super) const PAGE_SIZE: usize = 0x10000;
+pub(super) const TABLE_SIZE: usize = ICACHE_MMU_SIZE / core::mem::size_of::<u32>();
 
 extern "C" {
     /// Set DCache mmu mapping.

esp-hal/src/soc/esp32s3/psram.rs

@@ -151,6 +151,9 @@ pub(crate) fn init_psram(config: PsramConfig) {
         // bigger than a flash page - i.e. we will see an unmapped memory slot
         // start from the end and find the last mapped flash page
         let psram_start_index = mmu::last_mapped_index().map(|e| e + 1).unwrap_or(0);
+        if psram_start_index >= mmu::TABLE_SIZE {
+            panic!("PSRAM cannot be mapped as MMU table has no empty trailing entries");
+        }
         let start = mmu::index_to_data_address(psram_start_index);
         debug!("PSRAM start address = {:x}", start);