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Merged
merged 12 commits into from
Sep 6, 2024
Merged

Enable ESP32 HIL #1977

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216cc46
Enable ESP32 HIL
JurajSadel Aug 21, 2024
d18dc39
RMT fixed
JurajSadel Aug 23, 2024
35ee6d7
SPI DMA partially works, _pcnt tests not working
JurajSadel Aug 24, 2024
5d4fc3c
bckup
JurajSadel Sep 3, 2024
6e3b8a0
finish
JurajSadel Sep 5, 2024
74718ee
readme and cleanup
JurajSadel Sep 5, 2024
aafb88b
rebase + cleanup
JurajSadel Sep 5, 2024
34182d1
RMT S2 pin typo + clean forgotten comments
JurajSadel Sep 5, 2024
be3d38c
review comments
JurajSadel Sep 5, 2024
8a3ee1d
update 10000
JurajSadel Sep 5, 2024
2ff8b24
indentation
JurajSadel Sep 5, 2024
0f7035d
replace cfg gate with cfg_if
JurajSadel Sep 6, 2024
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6 changes: 6 additions & 0 deletions .github/workflows/hil.yml
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Expand Up @@ -86,6 +86,8 @@ jobs:
- soc: esp32h2
rust-target: riscv32imac-unknown-none-elf
# # Xtensa devices:
- soc: esp32
rust-target: xtensa-esp32-none-elf
- soc: esp32s2
rust-target: xtensa-esp32s2-none-elf
- soc: esp32s3
Expand Down Expand Up @@ -168,6 +170,10 @@ jobs:
host: armv7
hubs: "1-1"
# Xtensa devices:
- soc: esp32
runner: esp32-jtag
host: aarch64
hubs: "1 3"
- soc: esp32s2
runner: esp32s2-jtag
host: armv7
Expand Down
8 changes: 8 additions & 0 deletions hil-test/README.md
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Expand Up @@ -103,9 +103,17 @@ Our self-hosted runners have the following setup:
- `GPIO9` and `GPIO10` are connected.
- `GPIO43 (TX)` and `GPIO45` are connected.
- RPi: Raspbian 12 configured with the following [setup]
- ESP32 (`esp32-jtag`):
- Devkit: `ESP32-DevKitC-V4` connected via UART.
- `GPIO32` and `GPIO33` are I2C pins.
- `GPIO4` and `GPIO5` are connected.
- `GPIO26` and `GPIO27` are connected.
- Probe: `ESP-Prog` connected with the [following connections][connection_esp32]
- RPi: Raspbian 12 configured with the following [setup]

[connection_c2]: https://docs.espressif.com/projects/esp-idf/en/stable/esp32c2/api-guides/jtag-debugging/configure-other-jtag.html#configure-hardware
[connection_s2]: https://docs.espressif.com/projects/esp-idf/en/stable/esp32s2/api-guides/jtag-debugging/configure-other-jtag.html#configure-hardware
[connection_esp32]: https://docs.espressif.com/projects/esp-idf/en/stable/esp32/api-guides/jtag-debugging/configure-other-jtag.html#configure-hardware.html#configure-hardware
[`hil.yml`]: https://github.com/esp-rs/esp-hal/blob/main/.github/workflows/hil.yml
[setup]: #rpi-setup

Expand Down
8 changes: 7 additions & 1 deletion hil-test/src/lib.rs
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Expand Up @@ -30,6 +30,8 @@ macro_rules! i2c_pins {
cfg_if::cfg_if! {
if #[cfg(any(esp32s2, esp32s3))] {
($io.pins.gpio2, $io.pins.gpio3)
} else if #[cfg(esp32)] {
($io.pins.gpio32, $io.pins.gpio33)
} else if #[cfg(esp32c6)] {
($io.pins.gpio6, $io.pins.gpio7)
} else if #[cfg(esp32h2)] {
Expand All @@ -49,7 +51,11 @@ macro_rules! common_test_pins {
cfg_if::cfg_if! {
if #[cfg(any(esp32s2, esp32s3))] {
($io.pins.gpio9, $io.pins.gpio10)
} else {
}
else if #[cfg(esp32)] {
($io.pins.gpio26, $io.pins.gpio27)
}
else {
($io.pins.gpio2, $io.pins.gpio3)
}
}
Expand Down
18 changes: 11 additions & 7 deletions hil-test/tests/embassy_timers_executors.rs
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Expand Up @@ -8,21 +8,23 @@
#![no_main]

use embassy_time::{Duration, Ticker, Timer};
use esp_hal::{
interrupt::software::SoftwareInterruptControl,
peripherals::Peripherals,
prelude::*,
timer::{timg::TimerGroup, ErasedTimer, OneShotTimer, PeriodicTimer},
};
#[cfg(not(feature = "esp32"))]
use esp_hal::{
interrupt::software::SoftwareInterruptControl,
interrupt::Priority,
timer::systimer::{Alarm, FrozenUnit, Periodic, SystemTimer, Target},
timer::ErasedTimer,
};
use esp_hal::{
peripherals::Peripherals,
prelude::*,
timer::{timg::TimerGroup, OneShotTimer, PeriodicTimer},
};
#[cfg(not(feature = "esp32"))]
use esp_hal_embassy::InterruptExecutor;
use hil_test as _;

#[cfg(not(feature = "esp32"))]
macro_rules! mk_static {
($t:ty,$val:expr) => {{
static STATIC_CELL: static_cell::StaticCell<$t> = static_cell::StaticCell::new();
Expand Down Expand Up @@ -123,7 +125,9 @@ fn set_up_embassy_with_systimer(peripherals: Peripherals) {
#[embedded_test::tests(executor = esp_hal_embassy::Executor::new())]
mod test {
use super::*;
use crate::{test_cases::*, test_helpers::*};
use crate::test_cases::*;
#[cfg(not(feature = "esp32"))]
use crate::test_helpers::*;

#[init]
fn init() -> Peripherals {
Expand Down
4 changes: 2 additions & 2 deletions hil-test/tests/gpio.rs
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@@ -1,8 +1,8 @@
//! GPIO Test
//!
//! Folowing pins are used:
//! GPIO2 / GPIO9 (esp32s2 and esp32s3)
//! GPIO3 / GPIO10 (esp32s2 and esp32s3)
//! GPIO2 / GPIO9 (esp32s2 / esp32s3) / GPIO26 (esp32)
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Suggested change
//! GPIO2 / GPIO9 (esp32s2 / esp32s3) / GPIO26 (esp32)
//! GPIO2 / GPIO9 / GPIO26 (esp32s2 / esp32s3 / esp32)

But I really don't think we want to multiply the pin map information for each test and a readme 😅

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Well, I'm not sure :D I personally like the GPIO usage in the test description more rather than in the current README. If we want to keep it only in the README is the current format ok (it only says which chips are being used for all tests on a target) and for example S3 uses quite a lot of pins - so if I want to run a GPIO test I don't know which pins are used for that test from the current README. Maybe we can add a table with each test and which GPIOs are used in the test to README but still the test description seems the "easiest" to follow for me.

//! GPIO3 / GPIO10 (esp32s2 / esp32s3) / GPIO27 (esp32)
//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
//% FEATURES: generic-queue
Expand Down
6 changes: 4 additions & 2 deletions hil-test/tests/i2c.rs
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Expand Up @@ -4,12 +4,14 @@
//! SDA GPIO2 (esp32s2 and esp32s3)
//! GPIO6 (esp32c6)
//! GPIO18 (esp32c2)
//! GPIO4 (esp32, esp32h2 and esp32c3)
//! GPIO4 (esp32h2 and esp32c3)
//! GPIO32 (esp32)
//!
//! SCL GPIO3 (esp32s2 and esp32s3)
//! GPIO7 (esp32c6, esp32 and esp32c3)
//! GPIO7 (esp32c6 and esp32c3)
//! GPIO22 (esp32h2)
//! GPIO19 (esp32c2)
//! GPIO33 (esp32)

//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3

Expand Down
22 changes: 20 additions & 2 deletions hil-test/tests/i2s_async.rs
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Expand Up @@ -13,7 +13,7 @@
#![no_main]

use esp_hal::{
dma::{Dma, DmaChannel0, DmaPriority},
dma::{Dma, DmaPriority},
gpio::Io,
i2s::{asynch::*, DataFormat, I2s, I2sTx, Standard},
peripheral::Peripheral,
Expand All @@ -23,6 +23,17 @@ use esp_hal::{
};
use hil_test as _;

cfg_if::cfg_if! {
if #[cfg(any(
feature = "esp32",
feature = "esp32s2",
))] {
use esp_hal::dma::Spi2DmaChannel as DmaChannel0;
} else {
use esp_hal::dma::DmaChannel0;
}
}

const BUFFER_SIZE: usize = 2000;

#[derive(Clone)]
Expand Down Expand Up @@ -91,7 +102,14 @@ mod tests {
let mut io = Io::new(peripherals.GPIO, peripherals.IO_MUX);

let dma = Dma::new(peripherals.DMA);
let dma_channel = dma.channel0;

cfg_if::cfg_if! {
if #[cfg(any(feature = "esp32", feature = "esp32s2"))] {
let dma_channel = dma.spi2channel;
} else {
let dma_channel = dma.channel0;
}
}

let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) =
esp_hal::dma_circular_buffers!(BUFFER_SIZE, BUFFER_SIZE);
Expand Down
1 change: 1 addition & 0 deletions hil-test/tests/pcnt.rs
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Expand Up @@ -2,6 +2,7 @@
//!
//! It's assumed GPIO2 is connected to GPIO3
//! (GPIO9 and GPIO10 for esp32s2 and esp32s3)
//! (GPIO26 and GPIO27 for esp32)

//% CHIPS: esp32 esp32c6 esp32h2 esp32s2 esp32s3

Expand Down
2 changes: 1 addition & 1 deletion hil-test/tests/qspi_read.rs
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Expand Up @@ -7,7 +7,7 @@
//!
//! Connect MISO and GPIO pins.

//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
//% CHIPS: esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3

#![no_std]
#![no_main]
Expand Down
2 changes: 1 addition & 1 deletion hil-test/tests/qspi_write.rs
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Expand Up @@ -9,7 +9,7 @@
//!
//! Connect MOSI and PCNT pins.

//% CHIPS: esp32 esp32c6 esp32h2 esp32s2 esp32s3
//% CHIPS: esp32c6 esp32h2 esp32s2 esp32s3

#![no_std]
#![no_main]
Expand Down
2 changes: 1 addition & 1 deletion hil-test/tests/qspi_write_read.rs
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Expand Up @@ -9,7 +9,7 @@
//!
//! Connect MOSI/MISO and GPIO pins.

//% CHIPS: esp32 esp32c6 esp32h2 esp32s2 esp32s3
//% CHIPS: esp32c6 esp32h2 esp32s2 esp32s3

#![no_std]
#![no_main]
Expand Down
15 changes: 11 additions & 4 deletions hil-test/tests/rmt.rs
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Expand Up @@ -2,6 +2,7 @@
//!
//! It's assumed GPIO2 is connected to GPIO3
//! (GPIO9 and GPIO10 for esp32s2 and esp32s3)
//! (GPIO26 and GPIO27 for esp32)

//% CHIPS: esp32 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3

Expand Down Expand Up @@ -59,11 +60,16 @@ mod tests {
};

cfg_if::cfg_if! {
if #[cfg(any(feature = "esp32", feature = "esp32s2"))] {
if #[cfg(feature = "esp32")] {
let rx_channel = {
use esp_hal::rmt::RxChannelCreator;
rmt.channel1.configure(rx, rx_config).unwrap()
};
} else if #[cfg(feature = "esp32s2")] {
let rx_channel = {
use esp_hal::rmt::RxChannelCreator;
rmt.channel1.configure(rx, rx_config).unwrap()
};
} else if #[cfg(feature = "esp32s3")] {
let rx_channel = {
use esp_hal::rmt::RxChannelCreator;
Expand Down Expand Up @@ -101,11 +107,12 @@ mod tests {

let rx_transaction = rx_channel.receive(&mut rcv_data).unwrap();
let tx_transaction = tx_channel.transmit(&tx_data);
tx_transaction.wait().unwrap();

rx_transaction.wait().unwrap();
tx_transaction.wait().unwrap();

// the last two pulse-codes are the ones which wait for the timeout so they
// can't be equal
// the last two pulse-codes are the ones which wait for the timeout so
// they can't be equal
assert_eq!(&tx_data[..18], &rcv_data[..18]);
}
}
19 changes: 8 additions & 11 deletions hil-test/tests/spi_full_duplex.rs
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Expand Up @@ -2,9 +2,8 @@
//!
//! Folowing pins are used:
//! SCLK GPIO0
//! MISO GPIO2 / GPIO9 (esp32s2 and esp32s3)
//! MOSI GPIO3 / GPIO10 (esp32s2 and esp32s3)
//! CS GPIO8
//! MISO GPIO2 / GPIO9 (esp32s2 / esp32s3) / GPIO26 (esp32)
//! MOSI GPIO3 / GPIO10 (esp32s2 / esp32s3) / GPIO27 (esp32)
//!
//! Connect MISO and MOSI pins.

Expand Down Expand Up @@ -37,16 +36,14 @@ mod tests {
let peripherals = esp_hal::init(esp_hal::Config::default());

let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);

let sclk = io.pins.gpio0;
let (miso, mosi) = hil_test::common_test_pins!(io);
let cs = io.pins.gpio8;

let spi = Spi::new(peripherals.SPI2, 1000u32.kHz(), SpiMode::Mode0).with_pins(
Some(sclk),
Some(mosi),
Some(miso),
Some(cs),
);

let spi = Spi::new(peripherals.SPI2, 1000u32.kHz(), SpiMode::Mode0)
.with_sck(sclk)
.with_mosi(mosi)
.with_miso(miso);

Context { spi }
}
Expand Down
10 changes: 5 additions & 5 deletions hil-test/tests/spi_full_duplex_dma.rs
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Expand Up @@ -2,9 +2,8 @@
//!
//! Folowing pins are used:
//! SCLK GPIO0
//! MISO GPIO2 / GPIO9 (esp32s2 and esp32s3)
//! MOSI GPIO3 / GPIO10 (esp32s2 and esp32s3)
//! CS GPIO8
//! MISO GPIO2 / GPIO9 (esp32s2 / esp32s3) / GPIO26 (esp32)
//! MOSI GPIO3 / GPIO10 (esp32s2 / esp32s3) / GPIO27 (esp32)
//!
//! Connect MISO and MOSI pins.

Expand Down Expand Up @@ -57,7 +56,6 @@ mod tests {
let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
let sclk = io.pins.gpio0;
let (miso, mosi) = hil_test::common_test_pins!(io);
let cs = io.pins.gpio8;

let dma = Dma::new(peripherals.DMA);

Expand All @@ -70,7 +68,9 @@ mod tests {
}

let spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0)
.with_pins(Some(sclk), Some(mosi), Some(miso), Some(cs))
.with_sck(sclk)
.with_mosi(mosi)
.with_miso(miso)
.with_dma(dma_channel.configure(false, DmaPriority::Priority0));

Context { spi }
Expand Down
8 changes: 4 additions & 4 deletions hil-test/tests/spi_full_duplex_dma_async.rs
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Expand Up @@ -4,7 +4,6 @@
//! SCLK GPIO0
//! MOSI GPIO3 / GPIO10 (esp32s3)
//! MISO GPIO4
//! CS GPIO8
//!
//! PCNT GPIO2 / GPIO9 (esp32s3)
//! OUTPUT GPIO5 (helper to keep MISO LOW)
Expand All @@ -14,7 +13,7 @@
//!
//! Connect PCNT and MOSI, MISO and GPIO5 pins.

//% CHIPS: esp32 esp32c6 esp32h2 esp32s3
//% CHIPS: esp32c6 esp32h2 esp32s3
//% FEATURES: generic-queue

#![no_std]
Expand Down Expand Up @@ -78,7 +77,6 @@ mod tests {

let (mosi_mirror, mosi) = hil_test::common_test_pins!(io);
let miso = io.pins.gpio4;
let cs = io.pins.gpio8;
let mosi_mirror = mosi_mirror.degrade();

let mut out_pin = Output::new(io.pins.gpio5, Level::Low);
Expand All @@ -100,7 +98,9 @@ mod tests {
let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();

let spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0)
.with_pins(Some(sclk), Some(mosi), Some(miso), Some(cs))
.with_sck(sclk)
.with_mosi(mosi)
.with_miso(miso)
.with_dma(dma_channel.configure_for_async(false, DmaPriority::Priority0))
.with_buffers(dma_tx_buf, dma_rx_buf);

Expand Down
8 changes: 4 additions & 4 deletions hil-test/tests/spi_full_duplex_dma_pcnt.rs
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Expand Up @@ -3,7 +3,6 @@
//! Folowing pins are used:
//! SCLK GPIO0
//! MOSI GPIO3 / GPIO10 (esp32s3)
//! CS GPIO8
//! PCNT GPIO2 / GPIO9 (esp32s3)
//! OUTPUT GPIO5 (helper to keep MISO LOW)
//!
Expand All @@ -12,7 +11,7 @@
//!
//! Connect MISO and MOSI pins.

//% CHIPS: esp32 esp32c6 esp32h2 esp32s3
//% CHIPS: esp32c6 esp32h2 esp32s3

#![no_std]
#![no_main]
Expand Down Expand Up @@ -70,7 +69,6 @@ mod tests {
let sclk = io.pins.gpio0;
let (mosi_mirror, mosi) = hil_test::common_test_pins!(io);
let miso = io.pins.gpio4;
let cs = io.pins.gpio8;

let dma = Dma::new(peripherals.DMA);

Expand All @@ -83,7 +81,9 @@ mod tests {
}

let spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0)
.with_pins(Some(sclk), Some(mosi), Some(miso), Some(cs))
.with_sck(sclk)
.with_mosi(mosi)
.with_miso(miso)
.with_dma(dma_channel.configure(false, DmaPriority::Priority0));

let pcnt = Pcnt::new(peripherals.PCNT);
Expand Down
4 changes: 2 additions & 2 deletions hil-test/tests/spi_half_duplex_read.rs
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Expand Up @@ -2,9 +2,9 @@
//!
//! Folowing pins are used:
//! SCLK GPIO0
//! MISO GPIO2 / GPIO9 (esp32s2 and esp32s3)
//! MISO GPIO2 / GPIO9 (esp32s2 / esp32s3) / GPIO26 (esp32)
//!
//! GPIO GPIO3 / GPIO10 (esp32s2 and esp32s3)
//! GPIO GPIO3 / GPIO10 (esp32s2 / esp32s3) / GPIO27 (esp32)
//!
//! Connect MISO and GPIO pins.

Expand Down
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