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songruosongruo
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Merge branch 'feature/esp32h21_regi2c_support' into 'master'
feat(regi2c): add regi2c support for esp32h21 Closes IDF-11550 and IDF-11858 See merge request espressif/esp-idf!37369
2 parents 27d68f5 + 8262915 commit 0631340

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57 files changed

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‎components/bootloader_support/src/esp32c5/bootloader_esp32c5.c‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -86,7 +86,6 @@ static void bootloader_super_wdt_auto_feed(void)
8686
static inline void bootloader_hardware_init(void)
8787
{
8888
_regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
89-
regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-8667 Remove this?
9089
regi2c_ctrl_ll_master_configure_clock();
9190
}
9291

‎components/bootloader_support/src/esp32c61/bootloader_esp32c61.c‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -87,7 +87,6 @@ static void bootloader_super_wdt_auto_feed(void)
8787
static inline void bootloader_hardware_init(void)
8888
{
8989
_regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
90-
regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-9274 Remove this?
9190
regi2c_ctrl_ll_master_configure_clock();
9291
}
9392

‎components/bootloader_support/src/esp32h21/bootloader_esp32h21.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -89,8 +89,8 @@ static inline void bootloader_hardware_init(void)
8989
CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_RFPLL);
9090
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_FORCE_RFPLL);
9191

92-
//TODO: [ESP32H21] IDF-11550, regi2c atomic clock
93-
regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
92+
_regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
93+
regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-11548 Remove this?
9494
regi2c_ctrl_ll_master_configure_clock();
9595
}
9696

‎components/esp_hw_support/include/esp_private/regi2c_ctrl.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,6 @@
99
#include <stdint.h>
1010
#include "sdkconfig.h"
1111
#include "esp_rom_regi2c.h"
12-
#include "soc/regi2c_defs.h"
1312
#include "soc/soc_caps.h"
1413
#include "esp_private/periph_ctrl.h"
1514
#include "hal/regi2c_ctrl_ll.h"
@@ -20,13 +19,13 @@ extern "C" {
2019

2120
#ifdef BOOTLOADER_BUILD
2221

23-
// For bootloader, the strategy is to keep the analog i2c master clock always enabled if SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE (in bootloader_hardware_init())
22+
// For bootloader, the strategy is to keep the analog i2c master clock always enabled if ANA_I2C_MST_CLK_HAS_ROOT_GATING (in bootloader_hardware_init())
2423
#define ANALOG_CLOCK_ENABLE()
2524
#define ANALOG_CLOCK_DISABLE()
2625

2726
#else // !BOOTLOADER_BUILD
2827

29-
#if SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE
28+
#if ANA_I2C_MST_CLK_HAS_ROOT_GATING
3029
// This clock needs to be enabled for regi2c write/read, pll calibaration, PHY, RNG, ADC, etc.
3130
// Use reference count to manage the analog i2c master clock
3231
#define ANALOG_CLOCK_ENABLE() \
@@ -70,6 +69,7 @@ extern "C" {
7069
#define regi2c_ctrl_read_reg_mask regi2c_read_reg_mask_raw
7170
#define regi2c_ctrl_write_reg regi2c_write_reg_raw
7271
#define regi2c_ctrl_write_reg_mask regi2c_write_reg_mask_raw
72+
7373
#define REGI2C_ENTER_CRITICAL()
7474
#define REGI2C_EXIT_CRITICAL()
7575
#else
@@ -106,7 +106,7 @@ void regi2c_exit_critical(void);
106106
* Restore regi2c analog calibration related configuration registers.
107107
* This is a workaround, and is fixed on later chips
108108
*/
109-
#if REGI2C_ANA_CALI_PD_WORKAROUND
109+
#if REGI2C_LL_ANA_CALI_PD_WORKAROUND
110110
void regi2c_analog_cali_reg_read(void);
111111
void regi2c_analog_cali_reg_write(void);
112112
#endif //#if ADC_CALI_PD_WORKAROUND

‎components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,6 @@
1212
#include "modem/modem_syscon_reg.h"
1313
#include "modem/modem_lpcon_reg.h"
1414
#include "soc/i2c_ana_mst_reg.h"
15-
#include "soc/regi2c_defs.h"
1615
#include "soc/chip_revision.h"
1716
#include "hal/efuse_hal.h"
1817

‎components/esp_hw_support/lowpower/port/esp32c6/sleep_clock.c‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,13 @@
11
/*
2-
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
66

77
#include "esp_private/sleep_clock.h"
88
#include "soc/pcr_reg.h"
99
#include "soc/pmu_reg.h"
10-
#include "soc/regi2c_defs.h"
10+
#include "soc/i2c_ana_mst_reg.h"
1111
#include "modem/modem_lpcon_reg.h"
1212
#include "modem/modem_syscon_reg.h"
1313

@@ -19,18 +19,18 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
1919

2020
const static sleep_retention_entries_config_t pcr_regs_retention[] = {
2121
/* Enable i2c master clock */
22-
[0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(0), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(0) },
22+
[0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(0), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(0) },
2323
/* Start BBPLL self-calibration */
24-
[1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(1), I2C_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) },
25-
[2] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(2), I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) },
24+
[1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(1), I2C_ANA_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) },
25+
[2] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(2), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) },
2626
/* Wait calibration done */
27-
[3] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(3), I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE, I2C_MST_BBPLL_CAL_DONE, 1, 0), .owner = ENTRY(0) },
27+
[3] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(3), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE, I2C_MST_BBPLL_CAL_DONE, 1, 0), .owner = ENTRY(0) },
2828
/* Stop BBPLL self-calibration */
29-
[4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(4), I2C_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) },
30-
[5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) },
29+
[4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(4), I2C_ANA_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) },
30+
[5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) },
3131
/* Clock configuration retention */
32-
[6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(6), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
33-
[7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(7), PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
32+
[6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(6), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
33+
[7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(7), PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
3434
};
3535

3636
esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);

‎components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,6 @@
99
#include "soc/pcr_reg.h"
1010
#include "soc/pmu_reg.h"
1111
#include "soc/i2c_ana_mst_reg.h"
12-
#include "soc/regi2c_defs.h"
1312
#include "modem/modem_lpcon_reg.h"
1413
#include "modem/modem_syscon_reg.h"
1514

‎components/esp_hw_support/lowpower/port/esp32h2/sleep_clock.c‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,9 +6,7 @@
66

77
#include "esp_private/sleep_clock.h"
88
#include "soc/i2c_ana_mst_reg.h"
9-
#include "soc/regi2c_defs.h"
109
#include "soc/pcr_reg.h"
11-
#include "soc/regi2c_defs.h"
1210
#include "modem/modem_syscon_reg.h"
1311
#include "modem/modem_lpcon_reg.h"
1412

‎components/esp_hw_support/lowpower/port/esp32h21/sleep_clock.c‎

Lines changed: 10 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -6,9 +6,7 @@
66

77
#include "esp_private/sleep_clock.h"
88
#include "soc/i2c_ana_mst_reg.h"
9-
#include "soc/regi2c_defs.h"
109
#include "soc/pcr_reg.h"
11-
#include "soc/regi2c_defs.h"
1210
#include "modem/modem_syscon_reg.h"
1311
#include "modem/modem_lpcon_reg.h"
1412

@@ -21,20 +19,20 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
2119

2220
const static sleep_retention_entries_config_t pcr_regs_retention[] = {
2321
/* Enable i2c master clock */
24-
[0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(0), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(0) },
22+
[0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(0), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(0) },
2523
/* Start BBPLL self-calibration */
26-
[1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(1), I2C_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) },
27-
[2] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(2), I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) },
24+
[1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(1), I2C_ANA_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) },
25+
[2] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(2), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) },
2826
/* Wait calibration done */
29-
[3] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(3), I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE, I2C_MST_BBPLL_CAL_DONE, 1, 0), .owner = ENTRY(0) },
27+
[3] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(3), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE, I2C_MST_BBPLL_CAL_DONE, 1, 0), .owner = ENTRY(0) },
3028
/* Stop BBPLL self-calibration */
31-
[4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(4), I2C_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) },
32-
[5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) },
29+
[4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(4), I2C_ANA_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) },
30+
[5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) },
3331
/* Clock configuration retention */
34-
[6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(6), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
35-
[7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(7), PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
36-
[8] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(8), PCR_BUS_CLK_UPDATE_REG, PCR_BUS_CLOCK_UPDATE, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
37-
[9] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(9), PCR_BUS_CLK_UPDATE_REG, 0x0, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
32+
[6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(6), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
33+
[7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(7), PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
34+
[8] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(8), PCR_BUS_CLK_UPDATE_REG, PCR_BUS_CLOCK_UPDATE, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
35+
[9] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(9), PCR_BUS_CLK_UPDATE_REG, 0x0, PCR_BUS_CLOCK_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
3836
};
3937

4038
esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);

‎components/esp_hw_support/port/esp32p4/rtc_clk.c‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -599,9 +599,6 @@ void rtc_clk_mpll_configure(uint32_t xtal_freq, uint32_t mpll_freq, bool thread_
599599
_regi2c_ctrl_ll_master_enable_clock(true);
600600
} else {
601601
ANALOG_CLOCK_ENABLE();
602-
#if !BOOTLOADER_BUILD
603-
regi2c_enter_critical();
604-
#endif
605602
}
606603
/* MPLL calibration start */
607604
regi2c_ctrl_ll_mpll_calibration_start();
@@ -614,9 +611,6 @@ void rtc_clk_mpll_configure(uint32_t xtal_freq, uint32_t mpll_freq, bool thread_
614611
if (thread_safe) {
615612
_regi2c_ctrl_ll_master_enable_clock(false);
616613
} else {
617-
#if !BOOTLOADER_BUILD
618-
regi2c_exit_critical();
619-
#endif
620614
ANALOG_CLOCK_DISABLE();
621615
}
622616
s_cur_mpll_freq = mpll_freq;

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