Merge branch 'feature/esp32h4_clock_support' into 'master'

feat(clk): Add basic clock support for esp32h4

Closes IDF-12285, IDF-12912, and IDF-12499

See merge request espressif/esp-idf!40166

Author: songruo

Kconfig

@@ -149,7 +149,6 @@ mainmenu "Espressif IoT Development Framework Configuration"
         bool
         default "y" if IDF_TARGET="esp32h4"
         select IDF_TARGET_ARCH_RISCV
-        select IDF_ENV_FPGA
         select IDF_ENV_BRINGUP
 
     config IDF_TARGET_LINUX

components/bootloader/Kconfig.projbuild

@@ -39,6 +39,15 @@ menu "Bootloader config"
 
     orsource "Kconfig.log"
 
+    config BOOTLOADER_CPU_CLK_FREQ_MHZ
+        int
+        default 64 if IDF_TARGET_ESP32H2
+        default 48 if IDF_TARGET_ESP32H21 || IDF_TARGET_ESP32H4
+        default 90 if IDF_TARGET_ESP32P4
+        default 80
+        help
+            The CPU clock frequency to be at least raised to in 2nd bootloader. Invisible for users.
+
     menu "Serial Flash Configurations"
         config BOOTLOADER_SPI_CUSTOM_WP_PIN
             bool "Use custom SPI Flash WP Pin when flash pins set in eFuse (read help)"

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h21.c

@@ -81,10 +81,11 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
 
 static void IRAM_ATTR bootloader_flash_clock_init(void)
 {
-    // To raise the MSPI clock to 64MHz, needs to enable the 64MHz clock source, which is XTAL_X2_CLK
-    // (FPGA image fixed MSPI0/1 clock to 64MHz)
-    clk_ll_xtal_x2_enable();
-    _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_PLL_F64M);
+    // // To raise the MSPI clock to 64MHz, needs to enable the 64MHz clock source, which is XTAL_X2_CLK
+    // // (FPGA image fixed MSPI0/1 clock to 64MHz)
+    // clk_ll_xtal_x2_enable();
+    // _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_PLL_F64M);
+    _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_PLL_F48M);
 }
 
 static void update_flash_config(const esp_image_header_t *bootloader_hdr)

components/bootloader_support/src/bootloader_clock_init.c

@@ -34,7 +34,7 @@ __attribute__((weak)) void bootloader_clock_configure(void)
     esp_rom_output_tx_wait_idle(0);
 
     /* Set CPU to a higher certain frequency. Keep other clocks unmodified. */
-    int cpu_freq_mhz = CPU_CLK_FREQ_MHZ_BTLD;
+    int cpu_freq_mhz = CONFIG_BOOTLOADER_CPU_CLK_FREQ_MHZ;
 
 #if CONFIG_IDF_TARGET_ESP32
     /* On ESP32 rev 0, switching to 80/160 MHz if clock was previously set to
@@ -57,7 +57,7 @@ __attribute__((weak)) void bootloader_clock_configure(void)
         // RTC_SLOW clock source will be switched according to Kconfig selection at application startup
         clk_cfg.slow_clk_src = rtc_clk_slow_src_get();
         if (clk_cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_INVALID) {
-            clk_cfg.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW;
+            clk_cfg.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_DEFAULT;
         }
 
         // Use RTC_FAST clock source sel register field's default value, XTAL_DIV, for 2nd stage bootloader

components/bootloader_support/src/bootloader_random.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2010-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -26,16 +26,16 @@
 
 #if !defined CONFIG_IDF_TARGET_ESP32S3
   #if (defined CONFIG_IDF_TARGET_ESP32C6 || defined CONFIG_IDF_TARGET_ESP32H2)
-    #define RNG_CPU_WAIT_CYCLE_NUM (80 * 16) // Keep the byte sampling frequency in the ~62KHz range which has been
+    #define RNG_CPU_WAIT_CYCLE_NUM (CONFIG_BOOTLOADER_CPU_CLK_FREQ_MHZ * 16) // Keep the byte sampling frequency in the ~62KHz range which has been
                                              // tested.
   #elif CONFIG_IDF_TARGET_ESP32P4
     // bootloader tested with around 63 KHz bytes reading frequency
-    #define RNG_CPU_WAIT_CYCLE_NUM (CPU_CLK_FREQ_MHZ_BTLD * 16)
+    #define RNG_CPU_WAIT_CYCLE_NUM (CONFIG_BOOTLOADER_CPU_CLK_FREQ_MHZ * 16)
   #else
-    #define RNG_CPU_WAIT_CYCLE_NUM (80 * 32 * 2) /* extra factor of 2 is precautionary */
+    #define RNG_CPU_WAIT_CYCLE_NUM (CONFIG_BOOTLOADER_CPU_CLK_FREQ_MHZ * 32 * 2) /* extra factor of 2 is precautionary */
   #endif
 #else
-  #define RNG_CPU_WAIT_CYCLE_NUM (80 * 23) /* 45 KHz reading frequency is the maximum we have tested so far on S3 */
+  #define RNG_CPU_WAIT_CYCLE_NUM (CONFIG_BOOTLOADER_CPU_CLK_FREQ_MHZ * 23) /* 45 KHz reading frequency is the maximum we have tested so far on S3 */
 #endif
 
  __attribute__((weak)) void bootloader_fill_random(void *buffer, size_t length)

components/bootloader_support/src/esp32h4/bootloader_esp32h4.c

@@ -13,11 +13,9 @@
 #include "esp_rom_efuse.h"
 #include "esp_rom_serial_output.h"
 #include "esp_rom_sys.h"
-#include "esp_rom_spiflash.h"
 #include "soc/gpio_sig_map.h"
 #include "esp_cpu.h"
 #include "soc/rtc.h"
-#include "soc/spi_periph.h"
 #include "soc/cache_reg.h"
 #include "soc/io_mux_reg.h"
 #include "soc/pcr_reg.h"
@@ -28,8 +26,6 @@
 #include "bootloader_flash_config.h"
 #include "bootloader_mem.h"
 #include "esp_private/regi2c_ctrl.h"
-// #include "soc/regi2c_lp_bias.h"
-// #include "soc/regi2c_bias.h"
 #include "soc/hp_system_reg.h"
 #include "bootloader_console.h"
 #include "bootloader_flash_priv.h"
@@ -83,39 +79,18 @@ static void bootloader_super_wdt_auto_feed(void)
     REG_WRITE(LP_WDT_SWD_WPROTECT_REG, 0);
 }
 
-void spi_flash_din_num_set(uint8_t spi_num, uint8_t din_num)
-{
-    uint32_t reg_val = (REG_READ(SPI_MEM_DIN_NUM_REG(spi_num)) & (~(SPI_MEM_DIN0_NUM_M | SPI_MEM_DIN1_NUM_M | SPI_MEM_DIN2_NUM_M | SPI_MEM_DIN3_NUM_M | SPI_MEM_DIN4_NUM_M | SPI_MEM_DIN5_NUM_M | SPI_MEM_DIN6_NUM_M | SPI_MEM_DIN7_NUM_M | SPI_MEM_DINS_NUM_M)))
-        | (din_num << SPI_MEM_DIN0_NUM_S) | (din_num << SPI_MEM_DIN1_NUM_S) | (din_num << SPI_MEM_DIN2_NUM_S) | (din_num << SPI_MEM_DIN3_NUM_S)
-        | (din_num << SPI_MEM_DIN4_NUM_S) | (din_num << SPI_MEM_DIN5_NUM_S) | (din_num << SPI_MEM_DIN6_NUM_S) | (din_num << SPI_MEM_DIN7_NUM_S) | (din_num << SPI_MEM_DINS_NUM_S);
-    REG_WRITE(SPI_MEM_DIN_NUM_REG(spi_num), reg_val);
-    REG_SET_BIT(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_TIMING_CALI_UPDATE);
-}
-
-void spi_flash_extra_dummy_set(uint8_t spi_num, uint8_t extra_dummy)
-{
-    rom_spiflash_legacy_data->dummy_len_plus[spi_num] = extra_dummy;
-}
-
-/*
- * din mode     din_num      dummy
-    1           0            1
-    0           0            0
-    1           0            2
-    0           0            1
-    1           0            3
-    0           0            2
-    1           0            4
-    0           0            3
- */
 static inline void bootloader_hardware_init(void)
 {
-    // TODO: IDF-12285 RF disable?
+    /* Disable RF pll by default */
+    CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_RFPLL);
+    SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_FORCE_RFPLL);
 
+#if !CONFIG_IDF_ENV_FPGA
     /* Enable analog i2c master clock */
     _regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
-    regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-12285 Remove this?
+    regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-12313 Remove this?
     regi2c_ctrl_ll_master_configure_clock();
+#endif
 }
 
 static inline void bootloader_ana_reset_config(void)

components/esp_hw_support/port/esp32/include/soc/rtc.h

@@ -116,7 +116,7 @@ typedef struct rtc_clk_config_s {
  */
 #define RTC_CLK_CONFIG_DEFAULT() { \
     .xtal_freq = CONFIG_XTAL_FREQ, \
-    .cpu_freq_mhz = 80, \
+    .cpu_freq_mhz = CONFIG_BOOTLOADER_CPU_CLK_FREQ_MHZ, \
     .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \
     .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \
     .clk_8m_div = 0, \

components/esp_hw_support/port/esp32c2/include/soc/rtc.h

@@ -186,7 +186,7 @@ typedef struct {
  */
 #define RTC_CLK_CONFIG_DEFAULT() { \
     .xtal_freq = CONFIG_XTAL_FREQ, \
-    .cpu_freq_mhz = 80, \
+    .cpu_freq_mhz = CONFIG_BOOTLOADER_CPU_CLK_FREQ_MHZ, \
     .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \
     .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \
     .clk_rtc_clk_div = 0, \

components/esp_hw_support/port/esp32c3/include/soc/rtc.h

@@ -186,7 +186,7 @@ typedef struct {
  */
 #define RTC_CLK_CONFIG_DEFAULT() { \
     .xtal_freq = CONFIG_XTAL_FREQ, \
-    .cpu_freq_mhz = 80, \
+    .cpu_freq_mhz = CONFIG_BOOTLOADER_CPU_CLK_FREQ_MHZ, \
     .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \
     .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \
     .clk_rtc_clk_div = 0, \

components/esp_hw_support/port/esp32c5/include/soc/rtc.h

@@ -147,7 +147,7 @@ typedef struct {
  */
 #define RTC_CLK_CONFIG_DEFAULT() { \
     .xtal_freq = CONFIG_XTAL_FREQ, \
-    .cpu_freq_mhz = 80, \
+    .cpu_freq_mhz = CONFIG_BOOTLOADER_CPU_CLK_FREQ_MHZ, \
     .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \
     .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \
     .clk_rtc_clk_div = 0, \