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KainarxKainarx
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feat(gdma): support gdma retention on h4
1 parent e353f92 commit 3d08799

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4 files changed

+278
-5
lines changed

4 files changed

+278
-5
lines changed

‎components/esp_hw_support/test_apps/dma/main/test_async_memcpy.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -247,19 +247,19 @@ TEST_CASE("memory copy with dest address unaligned", "[async mcp]")
247247
printf("Testing memcpy by AHB GDMA\r\n");
248248
TEST_ESP_OK(esp_async_memcpy_install_gdma_ahb(&driver_config, &driver));
249249
test_memcpy_with_dest_addr_unaligned(driver, false, false);
250-
#if SOC_AHB_GDMA_SUPPORT_PSRAM
250+
#if SOC_AHB_GDMA_SUPPORT_PSRAM && SOC_SPIRAM_SUPPORTED
251251
test_memcpy_with_dest_addr_unaligned(driver, true, true);
252-
#endif // SOC_AHB_GDMA_SUPPORT_PSRAM
252+
#endif // SOC_AHB_GDMA_SUPPORT_PSRAM && SOC_SPIRAM_SUPPORTED
253253
TEST_ESP_OK(esp_async_memcpy_uninstall(driver));
254254
#endif // SOC_AHB_GDMA_SUPPORTED
255255

256256
#if SOC_AXI_GDMA_SUPPORTED
257257
printf("Testing memcpy by AXI GDMA\r\n");
258258
TEST_ESP_OK(esp_async_memcpy_install_gdma_axi(&driver_config, &driver));
259259
test_memcpy_with_dest_addr_unaligned(driver, false, false);
260-
#if SOC_AXI_GDMA_SUPPORT_PSRAM
260+
#if SOC_AXI_GDMA_SUPPORT_PSRAM && SOC_SPIRAM_SUPPORTED
261261
test_memcpy_with_dest_addr_unaligned(driver, true, true);
262-
#endif // SOC_AXI_GDMA_SUPPORT_PSRAM
262+
#endif // SOC_AXI_GDMA_SUPPORT_PSRAM && SOC_SPIRAM_SUPPORTED
263263
TEST_ESP_OK(esp_async_memcpy_uninstall(driver));
264264
#endif // SOC_AXI_GDMA_SUPPORTED
265265
}

‎components/soc/esp32h4/gdma_periph.c‎

Lines changed: 269 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -35,3 +35,272 @@ const gdma_signal_conn_t gdma_periph_signals = {
3535
}
3636
}
3737
};
38+
39+
#if SOC_PAU_SUPPORTED && SOC_GDMA_SUPPORT_SLEEP_RETENTION
40+
/* AHB_DMA Channel (Group0, Pair0) Registers Context
41+
Include: AHB_DMA_MISC_CONF_REG
42+
AHB_DMA_IN_INT_ENA_CH0_REG / AHB_DMA_OUT_INT_ENA_CH0_REG
43+
AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG
44+
AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_LINK_ADDR_CH0_REG
45+
AHB_DMA_IN_PRI_CH0_REG / AHB_DMA_IN_PERI_SEL_CH0_REG
46+
AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG
47+
AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG
48+
AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG
49+
AHB_DMA_OUT_PRI_CH0_REG / AHB_DMA_OUT_PERI_SEL_CH0_REG
50+
AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG
51+
52+
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
53+
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
54+
*/
55+
#define G0P0_RETENTION_REGS_CNT_0 19
56+
#define G0P0_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x8)
57+
#define G0P0_RETENTION_REGS_CNT_1 4
58+
#define G0P0_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x600)
59+
static const uint32_t g0p0_regs_map0[4] = {0x100001, 0xc0000080, 0xc000780c, 0x780c};
60+
static const uint32_t g0p0_regs_map1[4] = {0x17, 0x0, 0x0, 0x0};
61+
static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
62+
[0] = {
63+
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
64+
G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \
65+
G0P0_RETENTION_REGS_CNT_0, 0, 0, \
66+
g0p0_regs_map0[0], g0p0_regs_map0[1], \
67+
g0p0_regs_map0[2], g0p0_regs_map0[3]), \
68+
.owner = GDMA_RETENTION_ENTRY
69+
}, \
70+
[1] = {
71+
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
72+
G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \
73+
G0P0_RETENTION_REGS_CNT_1, 0, 0, \
74+
g0p0_regs_map1[0], g0p0_regs_map1[1], \
75+
g0p0_regs_map1[2], g0p0_regs_map1[3]), \
76+
.owner = GDMA_RETENTION_ENTRY
77+
}, \
78+
};
79+
80+
/* AHB_DMA Channel (Group0, Pair1) Registers Context
81+
Include: AHB_DMA_MISC_CONF_REG
82+
AHB_DMA_IN_INT_ENA_CH1_REG / AHB_DMA_OUT_INT_ENA_CH1_REG
83+
84+
AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG
85+
AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_LINK_ADDR_CH1_REG
86+
AHB_DMA_IN_PRI_CH1_REG / AHB_DMA_IN_PERI_SEL_CH1_REG
87+
AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG
88+
AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG
89+
AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG
90+
AHB_DMA_OUT_PRI_CH1_REG / AHB_DMA_OUT_PERI_SEL_CH1_REG
91+
AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG
92+
93+
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
94+
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
95+
*/
96+
97+
#define G0P1_RETENTION_REGS_CNT_0 3
98+
#define G0P1_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x18)
99+
#define G0P1_RETENTION_REGS_CNT_1 16
100+
#define G0P1_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x200)
101+
#define G0P1_RETENTION_REGS_CNT_2 4
102+
#define G0P1_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600)
103+
static const uint32_t g0p1_regs_map0[4] = {0x100001, 0x8, 0x0, 0x0};
104+
static const uint32_t g0p1_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0};
105+
static const uint32_t g0p1_regs_map2[4] = {0x17, 0x0, 0x0, 0x0};
106+
static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
107+
[0] = {
108+
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
109+
G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \
110+
G0P1_RETENTION_REGS_CNT_0, 0, 0, \
111+
g0p1_regs_map0[0], g0p1_regs_map0[1], \
112+
g0p1_regs_map0[2], g0p1_regs_map0[3]), \
113+
.owner = GDMA_RETENTION_ENTRY
114+
}, \
115+
[1] = {
116+
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
117+
G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \
118+
G0P1_RETENTION_REGS_CNT_1, 0, 0, \
119+
g0p1_regs_map1[0], g0p1_regs_map1[1], \
120+
g0p1_regs_map1[2], g0p1_regs_map1[3]), \
121+
.owner = GDMA_RETENTION_ENTRY
122+
}, \
123+
[2] = {
124+
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
125+
G0P1_RETENTION_MAP_BASE_2, G0P1_RETENTION_MAP_BASE_2, \
126+
G0P1_RETENTION_REGS_CNT_2, 0, 0, \
127+
g0p1_regs_map2[0], g0p1_regs_map2[1], \
128+
g0p1_regs_map2[2], g0p1_regs_map2[3]), \
129+
.owner = GDMA_RETENTION_ENTRY
130+
}, \
131+
};
132+
133+
/* AHB_DMA Channel (Group0, Pair2) Registers Context
134+
Include: AHB_DMA_MISC_CONF_REG
135+
AHB_DMA_IN_INT_ENA_CH2_REG / AHB_DMA_OUT_INT_ENA_CH2_REG
136+
137+
AHB_DMA_IN_CONF0_CH2_REG / AHB_DMA_IN_CONF1_CH2_REG
138+
AHB_DMA_IN_LINK_CH2_REG / AHB_DMA_IN_LINK_ADDR_CH2_REG
139+
AHB_DMA_IN_PRI_CH2_REG / AHB_DMA_IN_PERI_SEL_CH2_REG
140+
AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG
141+
AHB_DMA_OUT_CONF0_CH2_REG / AHB_DMA_OUT_CONF1_CH2_REG
142+
AHB_DMA_OUT_LINK_CH2_REG / AHB_DMA_OUT_LINK_ADDR_CH2_REG
143+
AHB_DMA_OUT_PRI_CH2_REG / AHB_DMA_OUT_PERI_SEL_CH2_REG
144+
AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_REG
145+
146+
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
147+
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
148+
*/
149+
#define G0P2_RETENTION_REGS_CNT_0 3
150+
#define G0P2_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x28)
151+
#define G0P2_RETENTION_REGS_CNT_1 16
152+
#define G0P2_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x300)
153+
#define G0P2_RETENTION_REGS_CNT_2 4
154+
#define G0P2_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600)
155+
static const uint32_t g0p2_regs_map0[4] = {0x80100001, 0x8, 0x0, 0x0};
156+
static const uint32_t g0p2_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0};
157+
static const uint32_t g0p2_regs_map2[4] = {0x17, 0x0, 0x0, 0x0};
158+
static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
159+
[0] = {
160+
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
161+
G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \
162+
G0P2_RETENTION_REGS_CNT_0, 0, 0, \
163+
g0p2_regs_map0[0], g0p2_regs_map0[1], \
164+
g0p2_regs_map0[2], g0p2_regs_map0[3]), \
165+
.owner = GDMA_RETENTION_ENTRY
166+
}, \
167+
[1] = {
168+
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
169+
G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \
170+
G0P2_RETENTION_REGS_CNT_1, 0, 0, \
171+
g0p2_regs_map1[0], g0p2_regs_map1[1], \
172+
g0p2_regs_map1[2], g0p2_regs_map1[3]), \
173+
.owner = GDMA_RETENTION_ENTRY
174+
}, \
175+
[2] = {
176+
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
177+
G0P2_RETENTION_MAP_BASE_2, G0P2_RETENTION_MAP_BASE_2, \
178+
G0P2_RETENTION_REGS_CNT_2, 0, 0, \
179+
g0p2_regs_map2[0], g0p2_regs_map2[1], \
180+
g0p2_regs_map2[2], g0p2_regs_map2[3]), \
181+
.owner = GDMA_RETENTION_ENTRY
182+
}, \
183+
};
184+
185+
/* AHB_DMA Channel (Group0, Pair3) Registers Context
186+
Include: AHB_DMA_MISC_CONF_REG
187+
AHB_DMA_IN_INT_ENA_CH3_REG / AHB_DMA_OUT_INT_ENA_CH3_REG
188+
189+
AHB_DMA_IN_CONF0_CH3_REG / AHB_DMA_IN_CONF1_CH3_REG
190+
AHB_DMA_IN_LINK_CH3_REG / AHB_DMA_IN_LINK_ADDR_CH3_REG
191+
AHB_DMA_IN_PRI_CH3_REG / AHB_DMA_IN_PERI_SEL_CH3_REG
192+
AHB_DMA_RX_CH_ARB_WEIGH_CH3_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH3_REG
193+
AHB_DMA_OUT_CONF0_CH3_REG / AHB_DMA_OUT_CONF1_CH3_REG
194+
AHB_DMA_OUT_LINK_CH3_REG / AHB_DMA_OUT_LINK_ADDR_CH3_REG
195+
AHB_DMA_OUT_PRI_CH3_REG / AHB_DMA_OUT_PERI_SEL_CH3_REG
196+
AHB_DMA_TX_CH_ARB_WEIGH_CH3_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH3_REG
197+
198+
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
199+
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
200+
*/
201+
#define G0P3_RETENTION_REGS_CNT_0 3
202+
#define G0P3_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x38)
203+
#define G0P3_RETENTION_REGS_CNT_1 16
204+
#define G0P3_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x400)
205+
#define G0P3_RETENTION_REGS_CNT_2 4
206+
#define G0P3_RETENTION_MAP_BASE_2 (DR_REG_AHB_DMA_BASE + 0x600)
207+
static const uint32_t g0p3_regs_map0[4] = {0x8100001, 0x8, 0x0, 0x0};
208+
static const uint32_t g0p3_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0};
209+
static const uint32_t g0p3_regs_map2[4] = {0x17, 0x0, 0x0, 0x0};
210+
static const regdma_entries_config_t gdma_g0p3_regs_retention[] = {
211+
[0] = {
212+
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
213+
G0P3_RETENTION_MAP_BASE_0, G0P3_RETENTION_MAP_BASE_0, \
214+
G0P3_RETENTION_REGS_CNT_0, 0, 0, \
215+
g0p3_regs_map0[0], g0p3_regs_map0[1], \
216+
g0p3_regs_map0[2], g0p3_regs_map0[3]), \
217+
.owner = GDMA_RETENTION_ENTRY
218+
}, \
219+
[1] = {
220+
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
221+
G0P3_RETENTION_MAP_BASE_1, G0P3_RETENTION_MAP_BASE_1, \
222+
G0P3_RETENTION_REGS_CNT_1, 0, 0, \
223+
g0p3_regs_map1[0], g0p3_regs_map1[1], \
224+
g0p3_regs_map1[2], g0p3_regs_map1[3]), \
225+
.owner = GDMA_RETENTION_ENTRY
226+
}, \
227+
[2] = {
228+
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
229+
G0P3_RETENTION_MAP_BASE_2, G0P3_RETENTION_MAP_BASE_2, \
230+
G0P3_RETENTION_REGS_CNT_2, 0, 0, \
231+
g0p3_regs_map2[0], g0p3_regs_map2[1], \
232+
g0p3_regs_map2[2], g0p3_regs_map2[3]), \
233+
.owner = GDMA_RETENTION_ENTRY
234+
}, \
235+
};
236+
237+
/* AHB_DMA Channel (Group0, Pair4) Registers Context
238+
Include: AHB_DMA_MISC_CONF_REG
239+
AHB_DMA_IN_INT_ENA_CH4_REG / AHB_DMA_OUT_INT_ENA_CH4_REG
240+
241+
AHB_DMA_IN_CONF0_CH4_REG / AHB_DMA_IN_CONF1_CH4_REG
242+
AHB_DMA_IN_LINK_CH4_REG / AHB_DMA_IN_LINK_ADDR_CH4_REG
243+
AHB_DMA_IN_PRI_CH4_REG / AHB_DMA_IN_PERI_SEL_CH4_REG
244+
AHB_DMA_RX_CH_ARB_WEIGH_CH4_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH4_REG
245+
AHB_DMA_OUT_CONF0_CH4_REG / AHB_DMA_OUT_CONF1_CH4_REG
246+
AHB_DMA_OUT_LINK_CH4_REG / AHB_DMA_OUT_LINK_ADDR_CH4_REG
247+
AHB_DMA_OUT_PRI_CH4_REG / AHB_DMA_OUT_PERI_SEL_CH4_REG
248+
AHB_DMA_TX_CH_ARB_WEIGH_CH4_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH4_REG
249+
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
250+
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
251+
*/
252+
#define G0P4_RETENTION_REGS_CNT_0 3
253+
#define G0P4_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x48)
254+
#define G0P4_RETENTION_REGS_CNT_1 20
255+
#define G0P4_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x500)
256+
static const uint32_t g0p4_regs_map0[4] = {0x900001, 0x8, 0x0, 0x0};
257+
static const uint32_t g0p4_regs_map1[4] = {0x1e033, 0x1e033, 0x17, 0x0};
258+
static const regdma_entries_config_t gdma_g0p4_regs_retention[] = {
259+
[0] = {
260+
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
261+
G0P4_RETENTION_MAP_BASE_0, G0P4_RETENTION_MAP_BASE_0, \
262+
G0P4_RETENTION_REGS_CNT_0, 0, 0, \
263+
g0p4_regs_map0[0], g0p4_regs_map0[1], \
264+
g0p4_regs_map0[2], g0p4_regs_map0[3]), \
265+
.owner = GDMA_RETENTION_ENTRY
266+
}, \
267+
[1] = {
268+
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
269+
G0P4_RETENTION_MAP_BASE_1, G0P4_RETENTION_MAP_BASE_1, \
270+
G0P4_RETENTION_REGS_CNT_1, 0, 0, \
271+
g0p4_regs_map1[0], g0p4_regs_map1[1], \
272+
g0p4_regs_map1[2], g0p4_regs_map1[3]), \
273+
.owner = GDMA_RETENTION_ENTRY
274+
}, \
275+
};
276+
277+
const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = {
278+
[0] = {
279+
[0] = {
280+
gdma_g0p0_regs_retention,
281+
ARRAY_SIZE(gdma_g0p0_regs_retention),
282+
SLEEP_RETENTION_MODULE_GDMA_CH0,
283+
},
284+
[1] = {
285+
gdma_g0p1_regs_retention,
286+
ARRAY_SIZE(gdma_g0p1_regs_retention),
287+
SLEEP_RETENTION_MODULE_GDMA_CH1,
288+
},
289+
[2] = {
290+
gdma_g0p2_regs_retention,
291+
ARRAY_SIZE(gdma_g0p2_regs_retention),
292+
SLEEP_RETENTION_MODULE_GDMA_CH2,
293+
},
294+
[3] = {
295+
gdma_g0p3_regs_retention,
296+
ARRAY_SIZE(gdma_g0p3_regs_retention),
297+
SLEEP_RETENTION_MODULE_GDMA_CH3,
298+
},
299+
[4] = {
300+
gdma_g0p4_regs_retention,
301+
ARRAY_SIZE(gdma_g0p4_regs_retention),
302+
SLEEP_RETENTION_MODULE_GDMA_CH4,
303+
},
304+
}
305+
};
306+
#endif // SOC_PAU_SUPPORTED && SOC_GDMA_SUPPORT_SLEEP_RETENTION

‎components/soc/esp32h4/include/soc/Kconfig.soc_caps.in‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -163,6 +163,10 @@ config SOC_GDMA_PAIRS_PER_GROUP_MAX
163163
int
164164
default 5
165165

166+
config SOC_GDMA_SUPPORT_SLEEP_RETENTION
167+
bool
168+
default y
169+
166170
config SOC_AHB_GDMA_SUPPORT_PSRAM
167171
bool
168172
default y

‎components/soc/esp32h4/include/soc/soc_caps.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -184,7 +184,7 @@
184184
#define SOC_GDMA_NUM_GROUPS_MAX 1U
185185
#define SOC_GDMA_PAIRS_PER_GROUP_MAX 5
186186
// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule TODO: [ESP32H4] IDF-12383
187-
// #define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 // TODO: [ESP32H4] IDF-12384
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#define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1
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#define SOC_AHB_GDMA_SUPPORT_PSRAM 1
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/*-------------------------- ETM CAPS --------------------------------------*/

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