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Bruce297Bruce297
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feat(esp32h21): refactor gpio_ll to use io_mux_struct
1 parent 760f134 commit d3acbe1

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6 files changed

+187
-67
lines changed

6 files changed

+187
-67
lines changed

‎components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -535,9 +535,6 @@ TEST_CASE("GPIO_set_output_level_get_input_level_test", "[gpio]")
535535
TEST_ASSERT_EQUAL_INT_MESSAGE(1, gpio_get_level(TEST_GPIO_EXT_IN_IO), "get level error! the level should be high!");
536536
}
537537

538-
#if !CONFIG_IDF_ENV_FPGA
539-
// On FPGA do not support GPIO pull down
540-
541538
// This test routes constant-high/low signal to pins, another way is to directly connect TEST_GPIO_EXT_IN_IO to
542539
// 3.3v or GND pin
543540
TEST_CASE("GPIO_get_level_from_fixed_voltage_test", "[gpio]")
@@ -564,6 +561,9 @@ TEST_CASE("GPIO_get_level_from_fixed_voltage_test", "[gpio]")
564561
TEST_ASSERT_EQUAL_INT_MESSAGE(0, level2, "get level error! the level should be low!");
565562
}
566563

564+
#if !CONFIG_IDF_ENV_FPGA
565+
// On FPGA do not support GPIO pull down
566+
567567
TEST_CASE("GPIO_io_pull_up/down_function", "[gpio]")
568568
{
569569
// First, ensure that the output IO will not affect the level

‎components/hal/esp32c5/include/hal/gpio_ll.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -259,7 +259,7 @@ static inline void gpio_ll_pin_filter_disable(gpio_dev_t *hw, uint32_t gpio_num)
259259
static inline void gpio_ll_pin_input_hysteresis_enable(gpio_dev_t *hw, uint32_t gpio_num)
260260
{
261261
// On ESP32C5, there is an efuse bit that controls the hysteresis enable or not for all IOs.
262-
// We are not going to use the hardware control in IDF for C5.
262+
// We are not going to use the hardware control for C5.
263263
// Therefore, we need to always switch to use software control first.
264264
// i.e. Swt hys_sel to 1, so that hys_en determines whether hysteresis is enabled or not
265265
IO_MUX.gpio[gpio_num].hys_sel = 1;

‎components/hal/esp32h21/include/hal/gpio_ll.h‎

Lines changed: 41 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -21,9 +21,10 @@
2121
#include "soc/gpio_struct.h"
2222
#include "soc/lp_aon_struct.h"
2323
#include "soc/pmu_struct.h"
24-
#include "soc/usb_serial_jtag_reg.h"
2524
#include "soc/pcr_struct.h"
2625
#include "soc/clk_tree_defs.h"
26+
#include "soc/io_mux_struct.h"
27+
#include "soc/usb_serial_jtag_struct.h"
2728
#include "hal/gpio_types.h"
2829
#include "hal/misc.h"
2930
#include "hal/assert.h"
@@ -48,18 +49,17 @@ extern "C" {
4849
static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num, gpio_io_config_t *io_config)
4950
{
5051
uint32_t bit_mask = 1 << gpio_num;
51-
uint32_t iomux_reg_val = REG_READ(IO_MUX_GPIO0_REG + (gpio_num * 4));
52-
io_config->pu = (iomux_reg_val & FUN_PU_M) >> FUN_PU_S;
53-
io_config->pd = (iomux_reg_val & FUN_PD_M) >> FUN_PD_S;
54-
io_config->ie = (iomux_reg_val & FUN_IE_M) >> FUN_IE_S;
52+
io_config->pu = IO_MUX.gpio[gpio_num].fun_wpu;
53+
io_config->pd = IO_MUX.gpio[gpio_num].fun_wpd;
54+
io_config->ie = IO_MUX.gpio[gpio_num].fun_ie;
5555
io_config->oe = (hw->enable.val & bit_mask) >> gpio_num;
5656
io_config->oe_ctrl_by_periph = !(hw->funcn_out_sel_cfg[gpio_num].funcn_oe_sel);
5757
io_config->oe_inv = hw->funcn_out_sel_cfg[gpio_num].funcn_oe_inv_sel;
5858
io_config->od = hw->pinn[gpio_num].pinn_pad_driver;
59-
io_config->drv = (gpio_drive_cap_t)((iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S);
60-
io_config->fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S;
59+
io_config->drv = (gpio_drive_cap_t)IO_MUX.gpio[gpio_num].fun_drv;
60+
io_config->fun_sel = IO_MUX.gpio[gpio_num].mcu_sel;
6161
io_config->sig_out = hw->funcn_out_sel_cfg[gpio_num].funcn_out_sel;
62-
io_config->slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S;
62+
io_config->slp_sel = IO_MUX.gpio[gpio_num].slp_sel;
6363
}
6464

6565
/**
@@ -70,7 +70,7 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num, gpio
7070
*/
7171
static inline void gpio_ll_pullup_en(gpio_dev_t *hw, gpio_num_t gpio_num)
7272
{
73-
REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU);
73+
IO_MUX.gpio[gpio_num].fun_wpu = 1;
7474
}
7575

7676
/**
@@ -88,10 +88,10 @@ static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
8888
// which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead.
8989
// TODO: read the specific efuse with efuse_ll.h
9090
if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
91-
SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE);
92-
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP);
91+
USB_SERIAL_JTAG.serial_jtag_conf0.serial_jtag_pad_pull_override = 1;
92+
USB_SERIAL_JTAG.serial_jtag_conf0.serial_jtag_dp_pullup = 0;
9393
}
94-
REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU);
94+
IO_MUX.gpio[gpio_num].fun_wpu = 0;
9595
}
9696

9797
/**
@@ -102,7 +102,7 @@ static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
102102
*/
103103
static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, gpio_num_t gpio_num)
104104
{
105-
REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD);
105+
IO_MUX.gpio[gpio_num].fun_wpd = 1;
106106
}
107107

108108
/**
@@ -114,7 +114,7 @@ static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, gpio_num_t gpio_num)
114114
__attribute__((always_inline))
115115
static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
116116
{
117-
REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD);
117+
IO_MUX.gpio[gpio_num].fun_wpd = 0;
118118
}
119119

120120
/**
@@ -215,7 +215,7 @@ static inline void gpio_ll_intr_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
215215
__attribute__((always_inline))
216216
static inline void gpio_ll_input_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
217217
{
218-
PIN_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
218+
IO_MUX.gpio[gpio_num].fun_ie = 0;
219219
}
220220

221221
/**
@@ -227,7 +227,7 @@ static inline void gpio_ll_input_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
227227
__attribute__((always_inline))
228228
static inline void gpio_ll_input_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
229229
{
230-
PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
230+
IO_MUX.gpio[gpio_num].fun_ie = 1;
231231
}
232232

233233
/**
@@ -238,7 +238,7 @@ static inline void gpio_ll_input_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
238238
*/
239239
static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num)
240240
{
241-
PIN_FILTER_EN(IO_MUX_GPIO0_REG + (gpio_num * 4));
241+
IO_MUX.gpio[gpio_num].filter_en = 1;
242242
}
243243

244244
/**
@@ -249,29 +249,7 @@ static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num)
249249
*/
250250
static inline void gpio_ll_pin_filter_disable(gpio_dev_t *hw, uint32_t gpio_num)
251251
{
252-
PIN_FILTER_DIS(IO_MUX_GPIO0_REG + (gpio_num * 4));
253-
}
254-
255-
/**
256-
* @brief Select gpio hysteresis control by efuse.
257-
*
258-
* @param hw Peripheral GPIO hardware instance address.
259-
* @param gpio_num GPIO number
260-
*/
261-
static inline void gpio_ll_pin_input_hysteresis_ctrl_sel_efuse(gpio_dev_t *hw, uint32_t gpio_num)
262-
{
263-
PIN_HYS_EN_SEL_EFUSE(IO_MUX_GPIO0_REG + (gpio_num * 4));
264-
}
265-
266-
/**
267-
* @brief Select gpio hysteresis control by software.
268-
*
269-
* @param hw Peripheral GPIO hardware instance address.
270-
* @param gpio_num GPIO number
271-
*/
272-
static inline void gpio_ll_pin_input_hysteresis_ctrl_sel_soft(gpio_dev_t *hw, uint32_t gpio_num)
273-
{
274-
PIN_HYS_EN_SEL_SOFT(IO_MUX_GPIO0_REG + (gpio_num * 4));
252+
IO_MUX.gpio[gpio_num].filter_en = 0;
275253
}
276254

277255
/**
@@ -282,7 +260,12 @@ static inline void gpio_ll_pin_input_hysteresis_ctrl_sel_soft(gpio_dev_t *hw, ui
282260
*/
283261
static inline void gpio_ll_pin_input_hysteresis_enable(gpio_dev_t *hw, uint32_t gpio_num)
284262
{
285-
PIN_HYS_SOFT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
263+
// On ESP32H21, there is an efuse bit that controls the hysteresis enable or not for all IOs.
264+
// We are not going to use the hardware control for H21.
265+
// Therefore, we need to always switch to use software control first.
266+
// i.e. Swt hys_sel to 1, so that hys_en determines whether hysteresis is enabled or not
267+
IO_MUX.gpio[gpio_num].hys_sel = 1;
268+
IO_MUX.gpio[gpio_num].hys_en = 1;
286269
}
287270

288271
/**
@@ -293,7 +276,8 @@ static inline void gpio_ll_pin_input_hysteresis_enable(gpio_dev_t *hw, uint32_t
293276
*/
294277
static inline void gpio_ll_pin_input_hysteresis_disable(gpio_dev_t *hw, uint32_t gpio_num)
295278
{
296-
PIN_HYS_SOFT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
279+
IO_MUX.gpio[gpio_num].hys_sel = 1;
280+
IO_MUX.gpio[gpio_num].hys_en = 0;
297281
}
298282

299283
/**
@@ -424,7 +408,7 @@ static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
424408
*/
425409
static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_drive_cap_t strength)
426410
{
427-
SET_PERI_REG_BITS(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, strength, FUN_DRV_S);
411+
IO_MUX.gpio[gpio_num].fun_drv = strength;
428412
}
429413

430414
/**
@@ -436,7 +420,7 @@ static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_
436420
*/
437421
static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_drive_cap_t *strength)
438422
{
439-
*strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, FUN_DRV_S);
423+
*strength = (gpio_drive_cap_t)(IO_MUX.gpio[gpio_num].fun_drv);
440424
}
441425

442426
/**
@@ -518,11 +502,11 @@ static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_n
518502
__attribute__((always_inline))
519503
static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func)
520504
{
521-
// Disable USB Serial JTAG if pins 26 or pins 27 needs to select an IOMUX function
505+
// Disable USB Serial JTAG if pins 17 or pins 18 needs to select an IOMUX function
522506
if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
523-
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
507+
USB_SERIAL_JTAG.serial_jtag_conf0.serial_jtag_usb_pad_enable = 0;
524508
}
525-
PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func);
509+
IO_MUX.gpio[gpio_num].mcu_sel = func;
526510
}
527511

528512
/**
@@ -594,7 +578,7 @@ static inline void gpio_ll_force_unhold_all(void)
594578
*/
595579
static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, gpio_num_t gpio_num)
596580
{
597-
PIN_SLP_SEL_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
581+
IO_MUX.gpio[gpio_num].slp_sel = 1;
598582
}
599583

600584
/**
@@ -606,7 +590,7 @@ static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, gpio_num_t gpio_num)
606590
*/
607591
static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
608592
{
609-
PIN_SLP_SEL_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
593+
IO_MUX.gpio[gpio_num].slp_sel = 0;
610594
}
611595

612596
/**
@@ -617,7 +601,7 @@ static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
617601
*/
618602
static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
619603
{
620-
PIN_SLP_PULLUP_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
604+
IO_MUX.gpio[gpio_num].mcu_wpu = 0;
621605
}
622606

623607
/**
@@ -628,7 +612,7 @@ static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
628612
*/
629613
static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, gpio_num_t gpio_num)
630614
{
631-
PIN_SLP_PULLUP_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
615+
IO_MUX.gpio[gpio_num].mcu_wpu = 1;
632616
}
633617

634618
/**
@@ -639,7 +623,7 @@ static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, gpio_num_t gpio_num)
639623
*/
640624
static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, gpio_num_t gpio_num)
641625
{
642-
PIN_SLP_PULLDOWN_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
626+
IO_MUX.gpio[gpio_num].mcu_wpd = 1;
643627
}
644628

645629
/**
@@ -650,9 +634,8 @@ static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, gpio_num_t gpio_num
650634
*/
651635
static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
652636
{
653-
PIN_SLP_PULLDOWN_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
637+
IO_MUX.gpio[gpio_num].mcu_wpd = 0;
654638
}
655-
656639
/**
657640
* @brief Disable GPIO input in sleep mode.
658641
*
@@ -661,7 +644,7 @@ static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_nu
661644
*/
662645
static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
663646
{
664-
PIN_SLP_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
647+
IO_MUX.gpio[gpio_num].mcu_ie = 0;
665648
}
666649

667650
/**
@@ -672,7 +655,7 @@ static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, gpio_num_t gpio_n
672655
*/
673656
static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
674657
{
675-
PIN_SLP_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
658+
IO_MUX.gpio[gpio_num].mcu_ie = 1;
676659
}
677660

678661
/**
@@ -683,7 +666,7 @@ static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, gpio_num_t gpio_nu
683666
*/
684667
static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
685668
{
686-
PIN_SLP_OUTPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
669+
IO_MUX.gpio[gpio_num].mcu_oe = 0;
687670
}
688671

689672
/**
@@ -694,7 +677,7 @@ static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, gpio_num_t gpio_
694677
*/
695678
static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
696679
{
697-
PIN_SLP_OUTPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
680+
IO_MUX.gpio[gpio_num].mcu_oe = 1;
698681
}
699682

700683
/**

‎components/soc/esp32h21/include/soc/Kconfig.soc_caps.in‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -235,10 +235,6 @@ config SOC_GPIO_PIN_COUNT
235235
int
236236
default 26
237237

238-
config SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE
239-
bool
240-
default y
241-
242238
config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
243239
bool
244240
default y

‎components/soc/esp32h21/include/soc/soc_caps.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -193,7 +193,6 @@
193193
// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
194194
// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8
195195
// #define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1
196-
#define SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE 1 // By default, hysteresis enable/disable is controlled by efuse
197196

198197
// GPIO peripheral has the ETM extension
199198
// #define SOC_GPIO_SUPPORT_ETM 1

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