Merge branch 'feat/support_gptimer_on_h4' into 'master'

feat(gptimer): support gptimer on esp32h4

Closes IDF-12373 and IDF-12374

See merge request espressif/esp-idf!38168

Author: Kainarx

components/driver/deprecated/timer_legacy.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -332,8 +332,8 @@ esp_err_t timer_init(timer_group_t group_num, timer_idx_t timer_num, const timer
     GPTIMER_CLOCK_SRC_ATOMIC() {
         // although `clk_src` is of `timer_src_clk_t` type, but it's binary compatible with `gptimer_clock_source_t`,
         // as the underlying enum entries come from the same `soc_module_clk_t`
-        timer_ll_set_clock_source(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, (gptimer_clock_source_t)clk_src);
-        timer_ll_enable_clock(hal->dev, timer_num, true);
+        timer_ll_set_clock_source(group_num, timer_num, (gptimer_clock_source_t)clk_src);
+        timer_ll_enable_clock(group_num, timer_num, true);
     }
     timer_ll_set_clock_prescale(hal->dev, timer_num, config->divider);
     timer_ll_set_count_direction(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, config->counter_dir);
@@ -362,7 +362,7 @@ esp_err_t timer_deinit(timer_group_t group_num, timer_idx_t timer_num)
 
     // disable the source clock
     GPTIMER_CLOCK_SRC_ATOMIC() {
-        timer_ll_enable_clock(hal->dev, hal->timer_id, false);
+        timer_ll_enable_clock(group_num, hal->timer_id, false);
     }
     TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
     timer_ll_enable_intr(hal->dev, TIMER_LL_EVENT_ALARM(timer_num), false);

components/driver/test_apps/legacy_timer_driver/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |

components/esp_driver_gptimer/src/gptimer.c

@@ -195,7 +195,7 @@ esp_err_t gptimer_del_timer(gptimer_handle_t timer)
     ESP_LOGD(TAG, "del timer (%d,%d)", group_id, timer_id);
     // disable the source clock
     GPTIMER_CLOCK_SRC_ATOMIC() {
-        timer_ll_enable_clock(hal->dev, hal->timer_id, false);
+        timer_ll_enable_clock(group_id, hal->timer_id, false);
     }
     timer_hal_deinit(hal);
     // recycle memory resource

components/esp_driver_gptimer/src/gptimer_common.c

@@ -90,7 +90,7 @@ esp_err_t gptimer_select_periph_clock(gptimer_t *timer, gptimer_clock_source_t s
 {
     uint32_t counter_src_hz = 0;
     int timer_id = timer->timer_id;
-
+    int group_id = timer->group->group_id;
     // TODO: [clk_tree] to use a generic clock enable/disable or acquire/release function for all clock source
 #if SOC_TIMER_GROUP_SUPPORT_RC_FAST
     if (src_clk == GPTIMER_CLK_SRC_RC_FAST) {
@@ -134,7 +134,7 @@ esp_err_t gptimer_select_periph_clock(gptimer_t *timer, gptimer_clock_source_t s
 #endif // CONFIG_IDF_TARGET_ESP32C2
 
     if (need_pm_lock) {
-        sprintf(timer->pm_lock_name, "gptimer_%d_%d", timer->group->group_id, timer_id); // e.g. gptimer_0_0
+        sprintf(timer->pm_lock_name, "gptimer_%d_%d", group_id, timer_id); // e.g. gptimer_0_0
         ESP_RETURN_ON_ERROR(esp_pm_lock_create(pm_lock_type, 0, timer->pm_lock_name, &timer->pm_lock),
                             TAG, "create pm lock failed");
     }
@@ -145,8 +145,8 @@ esp_err_t gptimer_select_periph_clock(gptimer_t *timer, gptimer_clock_source_t s
     // on some ESP chip, different peripheral's clock source setting are mixed in the same register
     // so we need to make this done in an atomic way
     GPTIMER_CLOCK_SRC_ATOMIC() {
-        timer_ll_set_clock_source(timer->hal.dev, timer_id, src_clk);
-        timer_ll_enable_clock(timer->hal.dev, timer_id, true);
+        timer_ll_set_clock_source(group_id, timer_id, src_clk);
+        timer_ll_enable_clock(group_id, timer_id, true);
     }
     timer->clk_src = src_clk;
     uint32_t prescale = counter_src_hz / resolution_hz; // potential resolution loss here

components/esp_driver_gptimer/test_apps/gptimer/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |

components/esp_hw_support/port/esp32h4/esp_clk_tree.c

@@ -27,23 +27,22 @@ uint32_t *freq_value)
     uint32_t clk_src_freq = 0;
     switch (clk_src) {
     case SOC_MOD_CLK_XTAL:
-        clk_src_freq = 32 * MHZ;
+        clk_src_freq = SOC_XTAL_FREQ_32M * MHZ;
         break;
-    case SOC_MOD_CLK_PLL_F80M:
-        clk_src_freq = CLK_LL_PLL_80M_FREQ_MHZ * MHZ;
+    case SOC_MOD_CLK_PLL_F48M:
+        clk_src_freq = CLK_LL_PLL_48M_FREQ_MHZ * MHZ;
         break;
-    case SOC_MOD_CLK_PLL_F160M:
-        clk_src_freq = CLK_LL_PLL_160M_FREQ_MHZ * MHZ;
+    case SOC_MOD_CLK_PLL_F64M:
+        clk_src_freq = CLK_LL_PLL_64M_FREQ_MHZ * MHZ;
         break;
-    case SOC_MOD_CLK_PLL_F240M:
-        clk_src_freq = CLK_LL_PLL_240M_FREQ_MHZ * MHZ;
+    case SOC_MOD_CLK_PLL_F96M:
+        clk_src_freq = CLK_LL_PLL_96M_FREQ_MHZ * MHZ;
         break;
     default:
         break;
     }
 
-    ESP_RETURN_ON_FALSE(clk_src_freq, ESP_FAIL, TAG,
-                        "freq shouldn't be 0, calibration failed");
+    ESP_RETURN_ON_FALSE(clk_src_freq, ESP_FAIL, TAG, "freq shouldn't be 0, calibration failed");
     *freq_value = clk_src_freq;
     return ESP_OK;
 }

components/esp_hw_support/port/esp32h4/rtc_clk.c

@@ -23,7 +23,7 @@
 
 static const char *TAG = "rtc_clk";
 
-// Current PLL frequency, in 480MHz. Zero if PLL is not enabled.
+// Current PLL frequency, in 96MHz. Zero if PLL is not enabled.
 static int s_cur_pll_freq;
 
 static uint32_t s_bbpll_digi_consumers_ref_count = 0; // Currently, it only tracks whether the 48MHz PHY clock is in-use by USB Serial/JTAG
@@ -57,7 +57,7 @@ void rtc_clk_32k_enable_external(void)
 
 void rtc_clk_32k_bootstrap(uint32_t cycle)
 {
-    /* No special bootstrapping needed for ESP32-C6, 'cycle' argument is to keep the signature
+    /* No special bootstrapping needed for ESP32-H4, 'cycle' argument is to keep the signature
      * same as for the ESP32. Just enable the XTAL here.
      */
     (void)cycle;
@@ -183,7 +183,7 @@ static void rtc_clk_cpu_freq_to_8m(void)
  */
 static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
 {
-    clk_ll_cpu_set_hs_divider(CLK_LL_PLL_480M_FREQ_MHZ / cpu_freq_mhz);
+    clk_ll_cpu_set_hs_divider(CLK_LL_PLL_96M_FREQ_MHZ / cpu_freq_mhz);
     clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
     esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
 }
@@ -206,20 +206,20 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
 
         source_freq_mhz = xtal_freq;
         source = SOC_CPU_CLK_SRC_XTAL;
-    } else if (freq_mhz == 80) {
+    } else if (freq_mhz == 16) {
         real_freq_mhz = freq_mhz;
         source = SOC_CPU_CLK_SRC_PLL;
-        source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ;
+        source_freq_mhz = CLK_LL_PLL_96M_FREQ_MHZ;
         divider = 6;
-    } else if (freq_mhz == 120) {
+    } else if (freq_mhz == 24) {
         real_freq_mhz = freq_mhz;
         source = SOC_CPU_CLK_SRC_PLL;
-        source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ;
+        source_freq_mhz = CLK_LL_PLL_96M_FREQ_MHZ;
         divider = 4;
-    } else if (freq_mhz == 160) {
+    } else if (freq_mhz == 32) {
         real_freq_mhz = freq_mhz;
         source = SOC_CPU_CLK_SRC_PLL;
-        source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ;
+        source_freq_mhz = CLK_LL_PLL_96M_FREQ_MHZ;
         divider = 3;
     } else {
         // unsupported frequency

components/esp_system/port/soc/esp32c6/clk.c

@@ -255,8 +255,8 @@ __attribute__((weak)) void esp_perip_clk_init(void)
         rmt_ll_enable_group_clock(0, false);
         ledc_ll_enable_clock(&LEDC, false);
         ledc_ll_enable_bus_clock(false);
-        timer_ll_enable_clock(&TIMERG0, 0, false);
-        timer_ll_enable_clock(&TIMERG1, 0, false);
+        timer_ll_enable_clock(0, 0, false);
+        timer_ll_enable_clock(1, 0, false);
         _timer_ll_enable_bus_clock(0, false);
         _timer_ll_enable_bus_clock(1, false);
         twai_ll_enable_clock(0, false);

components/esp_system/port/soc/esp32h2/clk.c

@@ -244,8 +244,8 @@ __attribute__((weak)) void esp_perip_clk_init(void)
         rmt_ll_enable_group_clock(0, false);
         ledc_ll_enable_clock(&LEDC, false);
         ledc_ll_enable_bus_clock(false);
-        timer_ll_enable_clock(&TIMERG0, 0, false);
-        timer_ll_enable_clock(&TIMERG1, 0, false);
+        timer_ll_enable_clock(0, 0, false);
+        timer_ll_enable_clock(1, 0, false);
         _timer_ll_enable_bus_clock(0, false);
         _timer_ll_enable_bus_clock(1, false);
         twai_ll_enable_clock(0, false);

components/esp_system/port/soc/esp32h4/Kconfig.cpu

@@ -1,6 +1,6 @@
 choice ESP_DEFAULT_CPU_FREQ_MHZ
     prompt "CPU frequency"
-    default ESP_DEFAULT_CPU_FREQ_MHZ_64 if IDF_ENV_FPGA
+    default ESP_DEFAULT_CPU_FREQ_MHZ_32 if IDF_ENV_FPGA
     help
         CPU frequency to be set on application startup.