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KainarxKainarx
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feat(gptimer): support gptimer on esp32h4
1 parent 1e30aa7 commit faacaaa

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21 files changed

+307
-177
lines changed

21 files changed

+307
-177
lines changed

‎components/driver/test_apps/legacy_timer_driver/README.md‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,2 +1,2 @@
1-
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
2-
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
1+
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
2+
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |

‎components/esp_driver_gptimer/test_apps/gptimer/README.md‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,2 +1,2 @@
1-
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
2-
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
1+
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
2+
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |

‎components/esp_hw_support/port/esp32h4/esp_clk_tree.c‎

Lines changed: 8 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -27,23 +27,22 @@ uint32_t *freq_value)
2727
uint32_t clk_src_freq = 0;
2828
switch (clk_src) {
2929
case SOC_MOD_CLK_XTAL:
30-
clk_src_freq = 32 * MHZ;
30+
clk_src_freq = SOC_XTAL_FREQ_32M * MHZ;
3131
break;
32-
case SOC_MOD_CLK_PLL_F80M:
33-
clk_src_freq = CLK_LL_PLL_80M_FREQ_MHZ * MHZ;
32+
case SOC_MOD_CLK_PLL_F48M:
33+
clk_src_freq = CLK_LL_PLL_48M_FREQ_MHZ * MHZ;
3434
break;
35-
case SOC_MOD_CLK_PLL_F160M:
36-
clk_src_freq = CLK_LL_PLL_160M_FREQ_MHZ * MHZ;
35+
case SOC_MOD_CLK_PLL_F64M:
36+
clk_src_freq = CLK_LL_PLL_64M_FREQ_MHZ * MHZ;
3737
break;
38-
case SOC_MOD_CLK_PLL_F240M:
39-
clk_src_freq = CLK_LL_PLL_240M_FREQ_MHZ * MHZ;
38+
case SOC_MOD_CLK_PLL_F96M:
39+
clk_src_freq = CLK_LL_PLL_96M_FREQ_MHZ * MHZ;
4040
break;
4141
default:
4242
break;
4343
}
4444

45-
ESP_RETURN_ON_FALSE(clk_src_freq, ESP_FAIL, TAG,
46-
"freq shouldn't be 0, calibration failed");
45+
ESP_RETURN_ON_FALSE(clk_src_freq, ESP_FAIL, TAG, "freq shouldn't be 0, calibration failed");
4746
*freq_value = clk_src_freq;
4847
return ESP_OK;
4948
}

‎components/esp_hw_support/port/esp32h4/rtc_clk.c‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@
2323

2424
static const char *TAG = "rtc_clk";
2525

26-
// Current PLL frequency, in 480MHz. Zero if PLL is not enabled.
26+
// Current PLL frequency, in 96MHz. Zero if PLL is not enabled.
2727
static int s_cur_pll_freq;
2828

2929
static uint32_t s_bbpll_digi_consumers_ref_count = 0; // Currently, it only tracks whether the 48MHz PHY clock is in-use by USB Serial/JTAG
@@ -57,7 +57,7 @@ void rtc_clk_32k_enable_external(void)
5757

5858
void rtc_clk_32k_bootstrap(uint32_t cycle)
5959
{
60-
/* No special bootstrapping needed for ESP32-C6, 'cycle' argument is to keep the signature
60+
/* No special bootstrapping needed for ESP32-H4, 'cycle' argument is to keep the signature
6161
* same as for the ESP32. Just enable the XTAL here.
6262
*/
6363
(void)cycle;
@@ -183,7 +183,7 @@ static void rtc_clk_cpu_freq_to_8m(void)
183183
*/
184184
static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
185185
{
186-
clk_ll_cpu_set_hs_divider(CLK_LL_PLL_480M_FREQ_MHZ / cpu_freq_mhz);
186+
clk_ll_cpu_set_hs_divider(CLK_LL_PLL_96M_FREQ_MHZ / cpu_freq_mhz);
187187
clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
188188
esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
189189
}
@@ -206,20 +206,20 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
206206

207207
source_freq_mhz = xtal_freq;
208208
source = SOC_CPU_CLK_SRC_XTAL;
209-
} else if (freq_mhz == 80) {
209+
} else if (freq_mhz == 16) {
210210
real_freq_mhz = freq_mhz;
211211
source = SOC_CPU_CLK_SRC_PLL;
212-
source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ;
212+
source_freq_mhz = CLK_LL_PLL_96M_FREQ_MHZ;
213213
divider = 6;
214-
} else if (freq_mhz == 120) {
214+
} else if (freq_mhz == 24) {
215215
real_freq_mhz = freq_mhz;
216216
source = SOC_CPU_CLK_SRC_PLL;
217-
source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ;
217+
source_freq_mhz = CLK_LL_PLL_96M_FREQ_MHZ;
218218
divider = 4;
219-
} else if (freq_mhz == 160) {
219+
} else if (freq_mhz == 32) {
220220
real_freq_mhz = freq_mhz;
221221
source = SOC_CPU_CLK_SRC_PLL;
222-
source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ;
222+
source_freq_mhz = CLK_LL_PLL_96M_FREQ_MHZ;
223223
divider = 3;
224224
} else {
225225
// unsupported frequency

‎components/esp_system/port/soc/esp32h4/Kconfig.cpu‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
choice ESP_DEFAULT_CPU_FREQ_MHZ
22
prompt "CPU frequency"
3-
default ESP_DEFAULT_CPU_FREQ_MHZ_64 if IDF_ENV_FPGA
3+
default ESP_DEFAULT_CPU_FREQ_MHZ_32 if IDF_ENV_FPGA
44
help
55
CPU frequency to be set on application startup.
66

‎components/hal/esp32h4/include/hal/clk_tree_ll.h‎

Lines changed: 9 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -27,12 +27,10 @@ extern "C" {
2727

2828
#define MHZ (1000000)
2929

30-
#define CLK_LL_PLL_80M_FREQ_MHZ (80)
31-
#define CLK_LL_PLL_120M_FREQ_MHZ (120)
32-
#define CLK_LL_PLL_160M_FREQ_MHZ (160)
33-
#define CLK_LL_PLL_240M_FREQ_MHZ (240)
34-
35-
#define CLK_LL_PLL_480M_FREQ_MHZ (480)
30+
#define CLK_LL_PLL_8M_FREQ_MHZ (8)
31+
#define CLK_LL_PLL_48M_FREQ_MHZ (48)
32+
#define CLK_LL_PLL_64M_FREQ_MHZ (64)
33+
#define CLK_LL_PLL_96M_FREQ_MHZ (96)
3634

3735
#define CLK_LL_XTAL32K_CONFIG_DEFAULT() { \
3836
.dac = 3, \
@@ -273,8 +271,8 @@ static inline __attribute__((always_inline)) bool clk_ll_rc32k_digi_is_enabled(v
273271
*/
274272
static inline __attribute__((always_inline)) uint32_t clk_ll_bbpll_get_freq_mhz(void)
275273
{
276-
// The target has a fixed 480MHz SPLL
277-
return CLK_LL_PLL_480M_FREQ_MHZ;
274+
// The target has a fixed 96MHz SPLL
275+
return CLK_LL_PLL_96M_FREQ_MHZ;
278276
}
279277

280278
/**
@@ -284,9 +282,9 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_bbpll_get_freq_mhz(
284282
*/
285283
static inline __attribute__((always_inline)) void clk_ll_bbpll_set_freq_mhz(uint32_t pll_freq_mhz)
286284
{
287-
// The target SPLL is fixed to 480MHz
285+
// The target SPLL is fixed to 96MHz
288286
// Do nothing
289-
HAL_ASSERT(pll_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ);
287+
HAL_ASSERT(pll_freq_mhz == CLK_LL_PLL_96M_FREQ_MHZ);
290288
}
291289

292290
/**
@@ -297,7 +295,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_freq_mhz(uint
297295
*/
298296
static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32_t pll_freq_mhz, uint32_t xtal_freq_mhz)
299297
{
300-
HAL_ASSERT(pll_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ);
298+
HAL_ASSERT(pll_freq_mhz == CLK_LL_PLL_96M_FREQ_MHZ);
301299
uint8_t div_ref;
302300
uint8_t div7_0;
303301
uint8_t dr1;

‎components/hal/esp32h4/include/hal/gpio_ll.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -515,7 +515,7 @@ static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src)
515515
case SOC_MOD_CLK_XTAL:
516516
PCR.iomux_clk_conf.iomux_func_clk_sel = 3;
517517
break;
518-
case SOC_MOD_CLK_PLL_F80M:
518+
case SOC_MOD_CLK_PLL_F48M:
519519
PCR.iomux_clk_conf.iomux_func_clk_sel = 1;
520520
break;
521521
default:

‎components/hal/esp32h4/include/hal/mwdt_ll.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -286,7 +286,7 @@ FORCE_INLINE_ATTR void mwdt_ll_set_clock_source(timg_dev_t *hw, mwdt_clock_sourc
286286
case MWDT_CLK_SRC_XTAL:
287287
clk_id = 0;
288288
break;
289-
case MWDT_CLK_SRC_PLL_F80M:
289+
case MWDT_CLK_SRC_PLL_F48M:
290290
clk_id = 1;
291291
break;
292292
case MWDT_CLK_SRC_RC_FAST:

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