fix: IDFGH-14772 where M5Stack CoreS3 uses GPIO 35 for MISO and LCD D/C (IDFGH-16776)

[jboynes]

Adopts approach used by M5GFX that enables/diables output during SPI transaction.

Description

As described in #15510, the M5Stack CoreS3 and CoreS3-SE use GPIO 35 as the MISO line on the peripheral bus and as the D/C output when communicating with the LCD module. This prevents use of the display and SPI peripherals like the W5500 base (and possible the SD card but that's not been tested).

In the M5GFX library, this is worked around by enabling/disabling the D/C output pin alongside CS in cs_control().

This patch adopts the same approach using the pre- and post- transaction callbacks in the LCD panel driver. It enables use of the LCD and W5500 when using the esp-bsp and ESP-IDF components rather then M5Unified (e.g. to use lgvl).

Related

#15510
Potentially esp-bsp #374

Testing

Tested on a CoreS3-SE with the M5Stack PoE LAN base
Without the patch, the w5500 fails to reset, after the patch both LCD and W5500 operate.

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Note

Enables the D/C GPIO before SPI transfers and disables it after to prevent conflicts on shared pins (e.g., MISO).

• Driver: components/esp_lcd/spi/esp_lcd_panel_io_spi.c
  • Pre-transaction (lcd_spi_pre_trans_cb): After setting D/C level, explicitly enable D/C GPIO output via gpio_ll_output_enable(&GPIO, dc_gpio_num).
  • Post-transaction (lcd_spi_post_trans_color_cb): Disable D/C GPIO output via gpio_ll_output_disable(&GPIO, dc_gpio_num) after color transfer completion.

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