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ollie-etlollie-etl
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Add optional io buffers
1 parent ec35151 commit c80a65a

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4 files changed

+63
-23
lines changed

4 files changed

+63
-23
lines changed

‎rtl/iddr.v‎

Lines changed: 19 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,8 @@ module iddr #
4040
// Use IODDR2 for Spartan-6
4141
parameter IODDR_STYLE = "IODDR2",
4242
// Width of register in bits
43-
parameter WIDTH = 1
43+
parameter WIDTH = 1,
44+
parameter INSERT_BUFFERS = "FALSE"
4445
)
4546
(
4647
input wire clk,
@@ -64,11 +65,22 @@ Provides a consistent input DDR flip flop across multiple FPGA families
6465
q2 _______X___________X____D1_____X____D3_____X____D5_____X_
6566
6667
*/
67-
68+
wire [WIDTH-1:0] d_int;
6869
genvar n;
6970

7071
generate
7172

73+
if (INSERT_BUFFERS == "TRUE") begin
74+
for (genvar i = 0; i < WIDTH; i++) begin
75+
IBUF IBUF_inst (
76+
.I(d[i]),
77+
.O(d_int[i])
78+
);
79+
end
80+
end else begin
81+
assign d_int = d;
82+
end
83+
7284
if (TARGET == "XILINX") begin
7385
for (n = 0; n < WIDTH; n = n + 1) begin : iddr
7486
if (IODDR_STYLE == "IODDR") begin
@@ -81,7 +93,7 @@ if (TARGET == "XILINX") begin
8193
.Q2(q2[n]),
8294
.C(clk),
8395
.CE(1'b1),
84-
.D(d[n]),
96+
.D(d_int[n]),
8597
.R(1'b0),
8698
.S(1'b0)
8799
);
@@ -98,7 +110,7 @@ if (TARGET == "XILINX") begin
98110
.C0(clk),
99111
.C1(~clk),
100112
.CE(1'b1),
101-
.D(d[n]),
113+
.D(d_int[n]),
102114
.R(1'b0),
103115
.S(1'b0)
104116
);
@@ -120,7 +132,7 @@ end else if (TARGET == "ALTERA") begin
120132
)
121133
altddio_in_inst (
122134
.aset(1'b0),
123-
.datain(d),
135+
.datain(d_int),
124136
.inclocken(1'b1),
125137
.inclock(clk),
126138
.aclr(1'b0),
@@ -141,11 +153,11 @@ end else begin
141153
reg [WIDTH-1:0] q_reg_2 = {WIDTH{1'b0}};
142154

143155
always @(posedge clk) begin
144-
d_reg_1 <= d;
156+
d_reg_1 <= d_int;
145157
end
146158

147159
always @(negedge clk) begin
148-
d_reg_2 <= d;
160+
d_reg_2 <= d_int;
149161
end
150162

151163
always @(posedge clk) begin

‎rtl/oddr.v‎

Lines changed: 17 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,8 @@ module oddr #
4040
// Use IODDR2 for Spartan-6
4141
parameter IODDR_STYLE = "IODDR2",
4242
// Width of register in bits
43-
parameter WIDTH = 1
43+
parameter WIDTH = 1,
44+
parameter INSERT_BUFFERS = "FALSE"
4445
)
4546
(
4647
input wire clk,
@@ -51,6 +52,7 @@ module oddr #
5152
output wire [WIDTH-1:0] q
5253
);
5354

55+
wire [WIDTH-1:0] q_int;
5456
/*
5557
5658
Provides a consistent output DDR flip flop across multiple FPGA families
@@ -77,7 +79,7 @@ if (TARGET == "XILINX") begin
7779
.SRTYPE("ASYNC")
7880
)
7981
oddr_inst (
80-
.Q(q[n]),
82+
.Q(q_int[n]),
8183
.C(clk),
8284
.CE(1'b1),
8385
.D1(d1[n]),
@@ -91,7 +93,7 @@ if (TARGET == "XILINX") begin
9193
.SRTYPE("ASYNC")
9294
)
9395
oddr_inst (
94-
.Q(q[n]),
96+
.Q(q_int[n]),
9597
.C0(clk),
9698
.C1(~clk),
9799
.CE(1'b1),
@@ -115,7 +117,7 @@ end else if (TARGET == "ALTERA") begin
115117
.outclocken(1'b1),
116118
.outclock(clk),
117119
.aclr(1'b0),
118-
.dataout(q)
120+
.dataout(q_int)
119121
);
120122
end else begin
121123
reg [WIDTH-1:0] d_reg_1 = {WIDTH{1'b0}};
@@ -136,9 +138,19 @@ end else begin
136138
q_reg <= d_reg_2;
137139
end
138140

139-
assign q = q_reg;
141+
assign q_int = q_reg;
140142
end
141143

144+
if (INSERT_BUFFERS == "TRUE") begin
145+
for (genvar i = 0; i < WIDTH; i++) begin
146+
OBUF OBUF_inst (
147+
.I(q_int[i]),
148+
.O(q[i])
149+
);
150+
end
151+
end else begin
152+
assign q = q_int;
153+
end
142154
endgenerate
143155

144156
endmodule

‎rtl/rgmii_phy_if.v‎

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,8 @@ module rgmii_phy_if #
4444
// Use BUFG for Virtex-5, Spartan-6, Ultrascale
4545
parameter CLOCK_INPUT_STYLE = "BUFG",
4646
// Use 90 degree clock for RGMII transmit ("TRUE", "FALSE")
47-
parameter USE_CLK90 = "TRUE"
47+
parameter USE_CLK90 = "TRUE",
48+
parameter INSERT_BUFFERS = "TRUE"
4849
)
4950
(
5051
// Reset, synchronous to gmii_gtx_clk
@@ -101,7 +102,8 @@ ssio_ddr_in #
101102
.TARGET(TARGET),
102103
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
103104
.IODDR_STYLE(IODDR_STYLE),
104-
.WIDTH(5)
105+
.WIDTH(5),
106+
.INSERT_BUFFERS(INSERT_BUFFERS)
105107
)
106108
rx_ssio_ddr_inst (
107109
.input_clk(rgmii_rxc),
@@ -209,7 +211,8 @@ end
209211
oddr #(
210212
.TARGET(TARGET),
211213
.IODDR_STYLE(IODDR_STYLE),
212-
.WIDTH(1)
214+
.WIDTH(1),
215+
.INSERT_BUFFERS(INSERT_BUFFERS)
213216
)
214217
clk_oddr_inst (
215218
.clk(USE_CLK90 == "TRUE" ? gmii_gtx_clk_90 : clk),
@@ -221,7 +224,8 @@ clk_oddr_inst (
221224
oddr #(
222225
.TARGET(TARGET),
223226
.IODDR_STYLE(IODDR_STYLE),
224-
.WIDTH(5)
227+
.WIDTH(5),
228+
.INSERT_BUFFERS(INSERT_BUFFERS)
225229
)
226230
data_oddr_inst (
227231
.clk(clk),

‎rtl/ssio_ddr_in.v‎

Lines changed: 19 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,8 @@ module ssio_ddr_in #
4444
// Use BUFG for Virtex-5, Spartan-6, Ultrascale
4545
parameter CLOCK_INPUT_STYLE = "BUFG",
4646
// Width of register in bits
47-
parameter WIDTH = 1
47+
parameter WIDTH = 1,
48+
parameter INSERT_BUFFERS = "FALSE"
4849
)
4950
(
5051
input wire input_clk,
@@ -57,11 +58,21 @@ module ssio_ddr_in #
5758
output wire [WIDTH-1:0] output_q2
5859
);
5960

61+
wire input_clk_int;
6062
wire clk_int;
6163
wire clk_io;
6264

6365
generate
6466

67+
if (INSERT_BUFFERS == "TRUE") begin
68+
IBUF IBUF_inst (
69+
.I(input_clk),
70+
.O(input_clk_int)
71+
);
72+
end else begin
73+
assign input_clk_int = input_clk;
74+
end
75+
6576
if (TARGET == "XILINX") begin
6677

6778
// use Xilinx clocking primitives
@@ -71,7 +82,7 @@ if (TARGET == "XILINX") begin
7182
// buffer RX clock
7283
BUFG
7384
clk_bufg (
74-
.I(input_clk),
85+
.I(input_clk_int),
7586
.O(clk_int)
7687
);
7788

@@ -81,7 +92,7 @@ if (TARGET == "XILINX") begin
8192

8293
end else if (CLOCK_INPUT_STYLE == "BUFR") begin
8394

84-
assign clk_int = input_clk;
95+
assign clk_int = input_clk_int;
8596

8697
// pass through RX clock to input buffers
8798
BUFIO
@@ -103,7 +114,7 @@ if (TARGET == "XILINX") begin
103114

104115
end else if (CLOCK_INPUT_STYLE == "BUFIO") begin
105116

106-
assign clk_int = input_clk;
117+
assign clk_int = input_clk_int;
107118

108119
// pass through RX clock to input buffers
109120
BUFIO
@@ -124,10 +135,10 @@ if (TARGET == "XILINX") begin
124135
end else begin
125136

126137
// pass through RX clock to input buffers
127-
assign clk_io = input_clk;
138+
assign clk_io = input_clk_int;
128139

129140
// pass through RX clock to logic
130-
assign clk_int = input_clk;
141+
assign clk_int = input_clk_int;
131142
assign output_clk = clk_int;
132143

133144
end
@@ -137,7 +148,8 @@ endgenerate
137148
iddr #(
138149
.TARGET(TARGET),
139150
.IODDR_STYLE(IODDR_STYLE),
140-
.WIDTH(WIDTH)
151+
.WIDTH(WIDTH),
152+
.INSERT_BUFFERS(INSERT_BUFFERS)
141153
)
142154
data_iddr_inst (
143155
.clk(clk_io),

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