idelay integration

Author: kavitha-etl

rtl/iddr.v

@@ -45,11 +45,19 @@ module iddr #
 )
 (
     input  wire             clk,
+    input  wire             rst,
+    input  wire             en, 
+    input  wire             en_vtc,
+    input  wire             inc,
+    input  wire             load,
+    input  wire [8:0]      cnt_value_in,
+    output wire [(WIDTH*9)-1:0]      cnt_value_out,
+    // Data input   
 
     input  wire [WIDTH-1:0] d,
 
     output wire [WIDTH-1:0] q1,
-    output wire [WIDTH-1:0] q2
+    output wire [WIDTH-1:0] q2,
 );
 
 /*
@@ -66,6 +74,7 @@ Provides a consistent input DDR flip flop across multiple FPGA families
 
 */
 wire [WIDTH-1:0] d_int;
+wire [WIDTH-1:0] delayed_data_int;
 genvar n;
 
 generate
@@ -83,6 +92,37 @@ end
 
 if (TARGET == "XILINX") begin
     for (n = 0; n < WIDTH; n = n + 1) begin : iddr
+      
+   IDELAYE3 #(
+      .CASCADE("NONE"),          // Cascade setting (MASTER, NONE, SLAVE_END, SLAVE_MIDDLE)
+      .DELAY_FORMAT("COUNT"),     // Units of the DELAY_VALUE (COUNT, TIME)
+      .DELAY_SRC("IDATAIN"),     // Delay input (DATAIN, IDATAIN)
+      .DELAY_TYPE("VARIABLE"),      // Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD)
+      .DELAY_VALUE(0),           // Input delay value setting
+      .IS_CLK_INVERTED(1'b0),    // Optional inversion for CLK
+      .IS_RST_INVERTED(1'b0),    // Optional inversion for RST
+      .REFCLK_FREQUENCY(125.0),  // IDELAYCTRL clock input frequency in MHz (200.0-800.0)
+      .SIM_DEVICE("ULTRASCALE_PLUS"), // Set the device version for simulation functionality (ULTRASCALE)
+      .UPDATE_MODE("ASYNC")      // Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC)
+   )
+   IDELAYE3_inst (
+      .CASC_OUT(),       // 1-bit output: Cascade delay output to ODELAY input cascade
+      .CNTVALUEOUT(cnt_value_out[(n*9)+8 : n*9 ]), // 9-bit output: Counter value output
+      .DATAOUT(delayed_data_int[n]),         // 1-bit output: Delayed data output
+      .CASC_IN(0),         // 1-bit input: Cascade delay input from slave ODELAY CASCADE_OUT
+      .CASC_RETURN(0), // 1-bit input: Cascade delay returning from slave ODELAY DATAOUT
+      .CE(en),                   // 1-bit input: Active-High enable increment/decrement input
+      .CLK(clk),                 // 1-bit input: Clock input
+      .CNTVALUEIN(cnt_value_in),   // 9-bit input: Counter value input
+      .DATAIN('0),           // 1-bit input: Data input from the logic
+      .EN_VTC(en_vtc),           // 1-bit input: Keep delay constant over VT
+      .IDATAIN(d_int[n]),         // 1-bit input: Data input from the IOBUF
+      .INC(inc),                 // 1-bit input: Increment / Decrement tap delay input
+      .LOAD(load),               // 1-bit input: Load DELAY_VALUE input
+      .RST(rst)                  // 1-bit input: Asynchronous Reset to the DELAY_VALUE
+   );
+
+
         if (IODDR_STYLE == "IODDR") begin
             IDDR #(
                 .DDR_CLK_EDGE("SAME_EDGE_PIPELINED"),
@@ -93,7 +133,7 @@ if (TARGET == "XILINX") begin
                 .Q2(q2[n]),
                 .C(clk),
                 .CE(1'b1),
-                .D(d_int[n]),
+                .D(),
                 .R(1'b0),
                 .S(1'b0)
             );
@@ -110,7 +150,7 @@ if (TARGET == "XILINX") begin
                 .C0(clk),
                 .C1(~clk),
                 .CE(1'b1),
-                .D(d_int[n]),
+                .D(delayed_data_int[n]),
                 .R(1'b0),
                 .S(1'b0)
             );

rtl/rgmii_phy_if.v

@@ -45,7 +45,7 @@ module rgmii_phy_if #
     parameter CLOCK_INPUT_STYLE = "BUFIO",
     // Use 90 degree clock for RGMII transmit ("TRUE", "FALSE")
     parameter USE_CLK90 = "TRUE",
-    parameter INSERT_BUFFERS = "FALSE"
+    parameter INSERT_BUFFERS = "TRUE"
 )
 (
     // Reset, synchronous to gmii_gtx_clk
@@ -90,7 +90,15 @@ module rgmii_phy_if #
     input  wire [1:0]  speed,
     output wire [47:0] debug_rgmii,
     output wire rx_rgmii_clk,
-    output wire rx_gmii_clk
+    output wire rx_gmii_clk,
+
+    input  wire             rst,
+    input  wire             en, 
+    input  wire             en_vtc,
+    input  wire             inc,
+    input  wire             load,
+    input  wire [8:0]      cnt_value_in,
+    output wire [(WIDTH*9)-1:0]      cnt_value_out
 
 
 
@@ -165,7 +173,14 @@ rx_ssio_ddr_inst (
     .input_d({rgmii_rd, rgmii_rx_ctl}),
     .output_clk(gmii_rx_clk),
     .output_q1({gmii_rxd[3:0], rgmii_rx_ctl_1}),
-    .output_q2({gmii_rxd[7:4], rgmii_rx_ctl_2})
+    .output_q2({gmii_rxd[7:4], rgmii_rx_ctl_2}),
+    .rst(rst),
+    .en(en), 
+    .en_vtc(en_vtc),
+    .inc(inc),
+    .load(load),
+    .cnt_value_in(cnt_value_in),
+    .cnt_value_out(cnt_value_out)
 );
 
 assign gmii_rx_dv = rgmii_rx_ctl_1;

rtl/ssio_ddr_in.v

@@ -55,7 +55,15 @@ module ssio_ddr_in #
     output wire             output_clk,
 
     output wire [WIDTH-1:0] output_q1,
-    output wire [WIDTH-1:0] output_q2
+    output wire [WIDTH-1:0] output_q2,
+
+    input  wire             rst,
+    input  wire             en, 
+    input  wire             en_vtc,
+    input  wire             inc,
+    input  wire             load,
+    input  wire [8:0]      cnt_value_in,
+    output wire [(WIDTH*9)-1:0]      cnt_value_out
 );
 
 wire input_clk_int;
@@ -145,6 +153,8 @@ end
 
 endgenerate
 
+
+
 iddr #(
     .TARGET(TARGET),
     .IODDR_STYLE(IODDR_STYLE),
@@ -155,7 +165,14 @@ data_iddr_inst (
     .clk(clk_io),
     .d(input_d),
     .q1(output_q1),
-    .q2(output_q2)
+    .q2(output_q2),
+    .rst(rst),
+    .en(en), 
+    .en_vtc(en_vtc),
+    .inc(inc),
+    .load(load),
+    .cnt_value_in(cnt_value_in),
+    .cnt_value_out(cnt_value_out)
 );
 
 endmodule