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ollie-etlollie-etl
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Simplify port naming
1 parent a541c73 commit de56d16

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+88
-89
lines changed

2 files changed

+88
-89
lines changed

‎rtl/eth_mac_1g_rgmii.v‎

Lines changed: 35 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -100,13 +100,13 @@ module eth_mac_1g_rgmii #
100100
input wire cfg_rx_enable
101101
);
102102

103-
wire [7:0] mac_gmii_rxd;
104-
wire mac_gmii_rx_dv;
105-
wire mac_gmii_rx_er;
106-
wire mac_gmii_tx_clk_en;
107-
wire [7:0] mac_gmii_txd;
108-
wire mac_gmii_tx_en;
109-
wire mac_gmii_tx_er;
103+
wire [7:0] gmii_rxd;
104+
wire gmii_rx_dv;
105+
wire gmii_rx_er;
106+
wire gmii_tx_clk_en;
107+
wire [7:0] gmii_txd;
108+
wire gmii_tx_en;
109+
wire gmii_tx_er;
110110

111111
reg [1:0] speed_reg = 2'b10;
112112
reg mii_select_reg = 1'b0;
@@ -189,39 +189,37 @@ rgmii_phy_if #(
189189
.USE_CLK90(USE_CLK90)
190190
)
191191
rgmii_phy_if_inst (
192-
.mac_gmii_gtx_clk(gtx_clk),
193-
.mac_gmii_gtx_clk_90(gtx_clk90),
192+
.gmii_gtx_clk(gtx_clk),
193+
.gmii_gtx_clk_90(gtx_clk90),
194194
.rst(gtx_rst),
195195

196-
.mac_gmii_rx_clk(rx_clk),
197-
.mac_gmii_rx_rst(rx_rst),
198-
.mac_gmii_rxd(mac_gmii_rxd),
199-
.mac_gmii_rx_dv(mac_gmii_rx_dv),
200-
.mac_gmii_rx_er(mac_gmii_rx_er),
201-
.mac_gmii_tx_rst(tx_rst),
202-
.mac_gmii_tx_clk_en(mac_gmii_tx_clk_en),
203-
.mac_gmii_txd(mac_gmii_txd),
204-
.mac_gmii_tx_en(mac_gmii_tx_en),
205-
.mac_gmii_tx_er(mac_gmii_tx_er),
206-
207-
.phy_rgmii_rxc(rgmii_rx_clk),
208-
.phy_rgmii_rd(rgmii_rxd),
209-
.phy_rgmii_rx_ctl(rgmii_rx_ctl),
210-
.phy_rgmii_txc(rgmii_tx_clk),
211-
.phy_rgmii_td(rgmii_txd),
212-
.phy_rgmii_tx_ctl(rgmii_tx_ctl),
196+
.gmii_rx_clk(rx_clk),
197+
.gmii_rx_rst(rx_rst),
198+
.gmii_rxd(gmii_rxd),
199+
.gmii_rx_dv(gmii_rx_dv),
200+
.gmii_rx_er(gmii_rx_er),
201+
.gmii_tx_rst(tx_rst),
202+
.gmii_tx_clk_en(gmii_tx_clk_en),
203+
.gmii_txd(gmii_txd),
204+
.gmii_tx_en(gmii_tx_en),
205+
.gmii_tx_er(gmii_tx_er),
206+
207+
.rgmii_rxc(rgmii_rx_clk),
208+
.rgmii_rd(rgmii_rxd),
209+
.rgmii_rx_ctl(rgmii_rx_ctl),
210+
.rgmii_txc(rgmii_tx_clk),
211+
.rgmii_td(rgmii_txd),
212+
.rgmii_tx_ctl(rgmii_tx_ctl),
213213

214214
.speed(speed)
215215
);
216216

217-
assign tx_clk = gtx_clk;
218-
219217
eth_mac_1g #(
220218
.ENABLE_PADDING(ENABLE_PADDING),
221219
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
222220
)
223221
eth_mac_1g_inst (
224-
.tx_clk(tx_clk),
222+
.tx_clk(gtx_clk),
225223
.tx_rst(tx_rst),
226224
.rx_clk(rx_clk),
227225
.rx_rst(rx_rst),
@@ -234,14 +232,15 @@ eth_mac_1g_inst (
234232
.rx_axis_tvalid(rx_axis_tvalid),
235233
.rx_axis_tlast(rx_axis_tlast),
236234
.rx_axis_tuser(rx_axis_tuser),
237-
.gmii_rxd(mac_gmii_rxd),
238-
.gmii_rx_dv(mac_gmii_rx_dv),
239-
.gmii_rx_er(mac_gmii_rx_er),
240-
.gmii_txd(mac_gmii_txd),
241-
.gmii_tx_en(mac_gmii_tx_en),
242-
.gmii_tx_er(mac_gmii_tx_er),
235+
.gmii_rxd(gmii_rxd),
236+
.gmii_rx_dv(gmii_rx_dv),
237+
.gmii_rx_er(gmii_rx_er),
238+
.gmii_gtx_clk(tx_clk),
239+
.gmii_txd(gmii_txd),
240+
.gmii_tx_en(gmii_tx_en),
241+
.gmii_tx_er(gmii_tx_er),
243242
.rx_clk_enable(1'b1),
244-
.tx_clk_enable(mac_gmii_tx_clk_en),
243+
.tx_clk_enable(gmii_tx_clk_en),
245244
.rx_mii_select(rx_mii_select_sync[1]),
246245
.tx_mii_select(tx_mii_select_sync[1]),
247246
.tx_error_underflow(tx_error_underflow),

‎rtl/rgmii_phy_if.v‎

Lines changed: 53 additions & 53 deletions
Original file line numberDiff line numberDiff line change
@@ -47,38 +47,38 @@ module rgmii_phy_if #
4747
parameter USE_CLK90 = "TRUE"
4848
)
4949
(
50-
// Reset, synchronous to mac_gmii_gtx_clk
50+
// Reset, synchronous to gmii_gtx_clk
5151
input wire rst,
5252

5353
/*
5454
* GMII interface to MAC
5555
*/
56-
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME mac_gmii, CAN_DEBUG false" *)
57-
(* X_INTERFACE_INFO = "xilinx.com:interface:gmii_rtl:1.0 mac_gmii RX_CLK" *) output wire mac_gmii_rx_clk,
58-
(* X_INTERFACE_INFO = "xilinx.com:interface:gmii_rtl:1.0 mac_gmii RXD" *) output wire [7:0] mac_gmii_rxd,
59-
(* X_INTERFACE_INFO = "xilinx.com:interface:gmii_rtl:1.0 mac_gmii RX_DV" *) output wire mac_gmii_rx_dv,
60-
(* X_INTERFACE_INFO = "xilinx.com:interface:gmii_rtl:1.0 mac_gmii RX_ER" *) output wire mac_gmii_rx_er,
61-
62-
(* X_INTERFACE_INFO = "xilinx.com:interface:gmii_rtl:1.0 mac_gmii GTX_CLK" *) input wire mac_gmii_gtx_clk,
63-
(* X_INTERFACE_INFO = "xilinx.com:interface:gmii_rtl:1.0 mac_gmii TXD" *) input wire [7:0] mac_gmii_txd,
64-
(* X_INTERFACE_INFO = "xilinx.com:interface:gmii_rtl:1.0 mac_gmii TX_EN" *) input wire mac_gmii_tx_en,
65-
(* X_INTERFACE_INFO = "xilinx.com:interface:gmii_rtl:1.0 mac_gmii TX_ER" *) input wire mac_gmii_tx_er,
56+
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME gmii, CAN_DEBUG false" *)
57+
(* X_INTERFACE_INFO = "xilinx.com:interface:gmii_rtl:1.0 gmii RX_CLK" *) output wire gmii_rx_clk,
58+
(* X_INTERFACE_INFO = "xilinx.com:interface:gmii_rtl:1.0 gmii RXD" *) output wire [7:0] gmii_rxd,
59+
(* X_INTERFACE_INFO = "xilinx.com:interface:gmii_rtl:1.0 gmii RX_DV" *) output wire gmii_rx_dv,
60+
(* X_INTERFACE_INFO = "xilinx.com:interface:gmii_rtl:1.0 gmii RX_ER" *) output wire gmii_rx_er,
61+
62+
(* X_INTERFACE_INFO = "xilinx.com:interface:gmii_rtl:1.0 gmii GTX_CLK" *) input wire gmii_gtx_clk,
63+
(* X_INTERFACE_INFO = "xilinx.com:interface:gmii_rtl:1.0 gmii TXD" *) input wire [7:0] gmii_txd,
64+
(* X_INTERFACE_INFO = "xilinx.com:interface:gmii_rtl:1.0 gmii TX_EN" *) input wire gmii_tx_en,
65+
(* X_INTERFACE_INFO = "xilinx.com:interface:gmii_rtl:1.0 gmii TX_ER" *) input wire gmii_tx_er,
6666
// These are non-standard gmii signals to control the MAC
67-
input wire mac_gmii_gtx_clk_90,
68-
output wire mac_gmii_rx_rst,
69-
output wire mac_gmii_tx_rst,
70-
output wire mac_gmii_tx_clk_en,
67+
input wire gmii_gtx_clk_90,
68+
output wire gmii_rx_rst,
69+
output wire gmii_tx_rst,
70+
output wire gmii_tx_clk_en,
7171

7272
/*
7373
* RGMII interface to PHY
7474
*/
75-
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME phy_rgmii, CAN_DEBUG false" *)
76-
(* X_INTERFACE_INFO = "xilinx.com:interface:rgmii_rtl:1.0 phy_rgmii RXC" *) input wire phy_rgmii_rxc,
77-
(* X_INTERFACE_INFO = "xilinx.com:interface:rgmii_rtl:1.0 phy_rgmii RD" *) input wire [3:0] phy_rgmii_rd,
78-
(* X_INTERFACE_INFO = "xilinx.com:interface:rgmii_rtl:1.0 phy_rgmii RX_CTL" *) input wire phy_rgmii_rx_ctl,
79-
(* X_INTERFACE_INFO = "xilinx.com:interface:rgmii_rtl:1.0 phy_rgmii TXC" *) output wire phy_rgmii_txc,
80-
(* X_INTERFACE_INFO = "xilinx.com:interface:rgmii_rtl:1.0 phy_rgmii TD" *) output wire [3:0] phy_rgmii_td,
81-
(* X_INTERFACE_INFO = "xilinx.com:interface:rgmii_rtl:1.0 phy_rgmii TX_CTL" *) output wire phy_rgmii_tx_ctl,
75+
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME rgmii, CAN_DEBUG false" *)
76+
(* X_INTERFACE_INFO = "xilinx.com:interface:rgmii_rtl:1.0 rgmii RXC" *) input wire rgmii_rxc,
77+
(* X_INTERFACE_INFO = "xilinx.com:interface:rgmii_rtl:1.0 rgmii RD" *) input wire [3:0] rgmii_rd,
78+
(* X_INTERFACE_INFO = "xilinx.com:interface:rgmii_rtl:1.0 rgmii RX_CTL" *) input wire rgmii_rx_ctl,
79+
(* X_INTERFACE_INFO = "xilinx.com:interface:rgmii_rtl:1.0 rgmii TXC" *) output wire rgmii_txc,
80+
(* X_INTERFACE_INFO = "xilinx.com:interface:rgmii_rtl:1.0 rgmii TD" *) output wire [3:0] rgmii_td,
81+
(* X_INTERFACE_INFO = "xilinx.com:interface:rgmii_rtl:1.0 rgmii TX_CTL" *) output wire rgmii_tx_ctl,
8282

8383
/*
8484
* Control
@@ -104,15 +104,15 @@ ssio_ddr_in #
104104
.WIDTH(5)
105105
)
106106
rx_ssio_ddr_inst (
107-
.input_clk(phy_rgmii_rxc),
108-
.input_d({phy_rgmii_rd, phy_rgmii_rx_ctl}),
109-
.output_clk(mac_gmii_rx_clk),
110-
.output_q1({mac_gmii_rxd[3:0], rgmii_rx_ctl_1}),
111-
.output_q2({mac_gmii_rxd[7:4], rgmii_rx_ctl_2})
107+
.input_clk(rgmii_rxc),
108+
.input_d({rgmii_rd, rgmii_rx_ctl}),
109+
.output_clk(gmii_rx_clk),
110+
.output_q1({gmii_rxd[3:0], rgmii_rx_ctl_1}),
111+
.output_q2({gmii_rxd[7:4], rgmii_rx_ctl_2})
112112
);
113113

114-
assign mac_gmii_rx_dv = rgmii_rx_ctl_1;
115-
assign mac_gmii_rx_er = rgmii_rx_ctl_1 ^ rgmii_rx_ctl_2;
114+
assign gmii_rx_dv = rgmii_rx_ctl_1;
115+
assign gmii_rx_er = rgmii_rx_ctl_1 ^ rgmii_rx_ctl_2;
116116

117117
// transmit
118118

@@ -174,34 +174,34 @@ reg gmii_clk_en = 1'b1;
174174
always @* begin
175175
if (speed == 2'b00) begin
176176
// 10M
177-
rgmii_txd_1 = mac_gmii_txd[3:0];
178-
rgmii_txd_2 = mac_gmii_txd[3:0];
177+
rgmii_txd_1 = gmii_txd[3:0];
178+
rgmii_txd_2 = gmii_txd[3:0];
179179
if (rgmii_tx_clk_1) begin
180-
rgmii_tx_ctl_1 = mac_gmii_tx_en ^ mac_gmii_tx_er;
181-
rgmii_tx_ctl_2 = mac_gmii_tx_en ^ mac_gmii_tx_er;
180+
rgmii_tx_ctl_1 = gmii_tx_en ^ gmii_tx_er;
181+
rgmii_tx_ctl_2 = gmii_tx_en ^ gmii_tx_er;
182182
end else begin
183-
rgmii_tx_ctl_1 = mac_gmii_tx_en;
184-
rgmii_tx_ctl_2 = mac_gmii_tx_en;
183+
rgmii_tx_ctl_1 = gmii_tx_en;
184+
rgmii_tx_ctl_2 = gmii_tx_en;
185185
end
186186
gmii_clk_en = rgmii_tx_clk_en;
187187
end else if (speed == 2'b01) begin
188188
// 100M
189-
rgmii_txd_1 = mac_gmii_txd[3:0];
190-
rgmii_txd_2 = mac_gmii_txd[3:0];
189+
rgmii_txd_1 = gmii_txd[3:0];
190+
rgmii_txd_2 = gmii_txd[3:0];
191191
if (rgmii_tx_clk_1) begin
192-
rgmii_tx_ctl_1 = mac_gmii_tx_en ^ mac_gmii_tx_er;
193-
rgmii_tx_ctl_2 = mac_gmii_tx_en ^ mac_gmii_tx_er;
192+
rgmii_tx_ctl_1 = gmii_tx_en ^ gmii_tx_er;
193+
rgmii_tx_ctl_2 = gmii_tx_en ^ gmii_tx_er;
194194
end else begin
195-
rgmii_tx_ctl_1 = mac_gmii_tx_en;
196-
rgmii_tx_ctl_2 = mac_gmii_tx_en;
195+
rgmii_tx_ctl_1 = gmii_tx_en;
196+
rgmii_tx_ctl_2 = gmii_tx_en;
197197
end
198198
gmii_clk_en = rgmii_tx_clk_en;
199199
end else begin
200200
// 1000M
201-
rgmii_txd_1 = mac_gmii_txd[3:0];
202-
rgmii_txd_2 = mac_gmii_txd[7:4];
203-
rgmii_tx_ctl_1 = mac_gmii_tx_en;
204-
rgmii_tx_ctl_2 = mac_gmii_tx_en ^ mac_gmii_tx_er;
201+
rgmii_txd_1 = gmii_txd[3:0];
202+
rgmii_txd_2 = gmii_txd[7:4];
203+
rgmii_tx_ctl_1 = gmii_tx_en;
204+
rgmii_tx_ctl_2 = gmii_tx_en ^ gmii_tx_er;
205205
gmii_clk_en = 1;
206206
end
207207
end
@@ -212,10 +212,10 @@ oddr #(
212212
.WIDTH(1)
213213
)
214214
clk_oddr_inst (
215-
.clk(USE_CLK90 == "TRUE" ? mac_gmii_gtx_clk_90 : clk),
215+
.clk(USE_CLK90 == "TRUE" ? gmii_gtx_clk_90 : clk),
216216
.d1(rgmii_tx_clk_1),
217217
.d2(rgmii_tx_clk_2),
218-
.q(phy_rgmii_txc)
218+
.q(rgmii_txc)
219219
);
220220

221221
oddr #(
@@ -227,16 +227,16 @@ data_oddr_inst (
227227
.clk(clk),
228228
.d1({rgmii_txd_1, rgmii_tx_ctl_1}),
229229
.d2({rgmii_txd_2, rgmii_tx_ctl_2}),
230-
.q({phy_rgmii_td, phy_rgmii_tx_ctl})
230+
.q({rgmii_td, rgmii_tx_ctl})
231231
);
232232

233-
assign clk = mac_gmii_gtx_clk;
233+
assign clk = gmii_gtx_clk;
234234

235-
assign mac_gmii_tx_clk_en = gmii_clk_en;
235+
assign gmii_tx_clk_en = gmii_clk_en;
236236

237237
// reset sync
238238
reg [3:0] tx_rst_reg = 4'hf;
239-
assign mac_gmii_tx_rst = tx_rst_reg[0];
239+
assign gmii_tx_rst = tx_rst_reg[0];
240240

241241
always @(posedge clk or posedge rst) begin
242242
if (rst) begin
@@ -247,9 +247,9 @@ always @(posedge clk or posedge rst) begin
247247
end
248248

249249
reg [3:0] rx_rst_reg = 4'hf;
250-
assign mac_gmii_rx_rst = rx_rst_reg[0];
250+
assign gmii_rx_rst = rx_rst_reg[0];
251251

252-
always @(posedge mac_gmii_rx_clk or posedge rst) begin
252+
always @(posedge gmii_rx_clk or posedge rst) begin
253253
if (rst) begin
254254
rx_rst_reg <= 4'hf;
255255
end else begin

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